Reducing the configuration loading time of a coarse grain multicontext reconfigurable device

Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo

Research output: Chapter in Book/Report/Conference proceedingChapter

2 Citations (Scopus)

Abstract

High speed and low cost configuration loading methods for a coarse grain multicontext reconfigurable device DRP(Dynamically Reconfigurable Processor) are proposed and implemented. In these methods, the configuration data is compressed on the host computer before loading, and decoded at the time of loading by circuits implemented on a part of logics. Unlike conventional reconfigurable device, the logic for decoder circuits is switched with application circuits immediately after loading in multicontext reconfigurable devices. Thus, the circuit does not use a real estate of the chip during the execution. Two compression methods LZSS-ARC and Selective coding are implemented and evaluated. LZSS-ARC achieves better compression ratio, while Selective coding can work at the same frequency of the data loading.

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
EditorsPeter Y. K. Cheung, George A. Constantinides, Jose T. de Sousa
PublisherSpringer Verlag
Pages171-180
Number of pages10
ISBN (Electronic)3540408223, 9783540408222
DOIs
Publication statusPublished - 2003

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2778
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

Fingerprint

Dive into the research topics of 'Reducing the configuration loading time of a coarse grain multicontext reconfigurable device'. Together they form a unique fingerprint.

Cite this