Reducing the configuration loading time of a coarse grain multicontext reconfigurable device

Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo

Research output: Contribution to journalArticle

15 Citations (Scopus)

Abstract

High speed and low cost configuration loading methods for a coarse grain multicontext reconfigurable device DRP(Dynamically Reconfigurable Processor) are proposed and implemented. In these methods, the configuration data is compressed on the host computer before loading, and decoded at the time of loading by circuits implemented on a part of logics. Unlike conventional reconfigurable device, the logic for decoder circuits is switched with application circuits immediately after loading in multicontext reconfigurable devices. Thus, the circuit does not use a real estate of the chip during the execution. Two compression methods LZSS-ARC and Selective coding are implemented and evaluated. LZSS-ARC achieves better compression ratio, while Selective coding can work at the same frequency of the data loading.

Original languageEnglish
Pages (from-to)171-180
Number of pages10
JournalLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2778
Publication statusPublished - 2003

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AIDS-Related Complex
Equipment and Supplies
Configuration
Networks (circuits)
Compression
Coding
Logic
Costs and Cost Analysis
Immediately
High Speed
Chip
Costs

ASJC Scopus subject areas

  • Computer Science(all)
  • Biochemistry, Genetics and Molecular Biology(all)
  • Theoretical Computer Science

Cite this

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