TY - GEN
T1 - Refinements in Data Manipulation Method for Coarse Grained Reconfigurable Architectures
AU - Kojima, Takuya
AU - Amano, Hideharu
N1 - Funding Information:
ACKNOWLEDGMENT This work is supported by VLSI Design and Education Center(VDEC), the University of Tokyo in collaboration with Synopsys, Inc and Cadence Design Systems, Inc.
Funding Information:
This work is partially supported by JSPS KAKENHI B Grant Number 18H03215 and JSPS KAKENHI Grant Number 19J21493.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - Coarse-grained reconfigurable architectures (CGRAs) is one of the suitable devices for IoT (Internet of Things) and edge-computing because of their high energy efficiency and programmability. The CGRAs process a compute-intensive part of an application program (especially a loop part) more efficiently than general purpose processors. CMA (Cool Mega Array) is an energy-conscious CGRA with a task-level reconfiguration instead of a cycle-level one. However, the CMA faces some limitations related to data management because of the aggressive pursuit of power saving. In this paper, we introduce a new CMA architecture VPCMA2 to relax the constraints and to improve energy efficiency. Then, we implement it with a 65-nm process technology to evaluate a hardware overhead due to the improvement. According to the evaluation results, the new design does not influence its maximum operating frequency. Although new functionalities brought about 17% power overhead and 10% area overhead, a remarkable improvement of application mappability and data handling was achieved.
AB - Coarse-grained reconfigurable architectures (CGRAs) is one of the suitable devices for IoT (Internet of Things) and edge-computing because of their high energy efficiency and programmability. The CGRAs process a compute-intensive part of an application program (especially a loop part) more efficiently than general purpose processors. CMA (Cool Mega Array) is an energy-conscious CGRA with a task-level reconfiguration instead of a cycle-level one. However, the CMA faces some limitations related to data management because of the aggressive pursuit of power saving. In this paper, we introduce a new CMA architecture VPCMA2 to relax the constraints and to improve energy efficiency. Then, we implement it with a 65-nm process technology to evaluate a hardware overhead due to the improvement. According to the evaluation results, the new design does not influence its maximum operating frequency. Although new functionalities brought about 17% power overhead and 10% area overhead, a remarkable improvement of application mappability and data handling was achieved.
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U2 - 10.1109/ReCoSoC48741.2019.9034924
DO - 10.1109/ReCoSoC48741.2019.9034924
M3 - Conference contribution
AN - SCOPUS:85101149593
T3 - Proceedings - 2019 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2019
SP - 113
EP - 120
BT - Proceedings - 2019 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2019
A2 - Fornaciari, William
A2 - Novo, David
A2 - Indrusiak, Leandro Soares
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2019
Y2 - 1 July 2019 through 3 July 2019
ER -
