Responsive multithreaded processor for distributed real-time processing

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Responsive MultiThreaded (RMT) Processor is a processor chip that integrates almost all functions for parallel/distributed real-time systems such as robots, intelligent rooms/buildings, amusement systems, etc. Concretely, the RMT Processor integrates a real-time processing core (RMT PU), a real-time communication (five sets of Responsive Links), computer I/O peripherals (DDR SDRAM I/Fs, DMAC, PCI-X, USB2.0, IEEE1394, etc.), and control I/O peripherals (PWM generators, pulse counters, etc.). The design rule of the RMT Processor is TSMC 0.13μm CMOS Cu 1P8M and its die size is 100 mm2. The RMTPU can execute eight prioritized threads simultaneously by using the SMT architecture based on priority, called the RMT architecture. Priority of real-time systems is introduced into all functional units including cache systems, a fetch unit, an issue unit, execution units, etc., so that the RMTPU can guarantee the real-time execution of the prioritized threads. If a resource conflict occurs at each functional unit, the higher priority thread can overtake the lower priority threads at the functional unit. So the RMT PU is like an SMT core with priority to execute threads simultaneously in order of priority set by a real-time operating system. The RMT PU has the hierarchical storage of thread states. The RMTPU has eight hardware contexts as the first level (native) register sets to execute the eight prioritized threads simultaneously. The RMT PU also has a context cache that can save 32 hardware contexts so as to handle and execute 40 prioritized threads concurrently by hardware.

Original languageEnglish
Title of host publicationProceedings - International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2006
Pages44-54
Number of pages11
DOIs
Publication statusPublished - 2006 Dec 1
EventInternational Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2006 - Kohala Coast, HI, United States
Duration: 2006 Jan 232006 Jan 25

Publication series

NameProceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Other

OtherInternational Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2006
CountryUnited States
CityKohala Coast, HI
Period06/1/2306/1/25

ASJC Scopus subject areas

  • Computer Science(all)

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  • Cite this

    Yamasaki, N. (2006). Responsive multithreaded processor for distributed real-time processing. In Proceedings - International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, IWIA 2006 (pp. 44-54). [4089355] (Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems). https://doi.org/10.1109/IWIAS.2006.36