TY - GEN
T1 - RT-libSGM
T2 - 12th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2022
AU - Wei, Kaijie
AU - Kuno, Yuki
AU - Arai, Masatoshi
AU - Amano, Hideharu
N1 - Funding Information:
This work was supported by JST CREST Grant Number JP-MJCR19K1, Japan and JST SPRING, Grant Number JPMJSP2123.
Publisher Copyright:
© 2022 ACM.
PY - 2022/6/9
Y1 - 2022/6/9
N2 - Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-programmable gate array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation running on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the original design (libSGM), when working on the Tegra X2 GPU, RT-libSGM runs 2 × faster at a lower energy cost.
AB - Stereo depth estimation has become an attractive topic in the computer vision field. Although various algorithms strive to optimize the speed and the precision of estimation, the energy cost of a system is also an essential metric for an embedded system. Among these various algorithms, Semi-Global Matching (SGM) has been a popular choice for some real-world applications because of its accuracy-and-speed balance. However, its power consumption makes it difficult to be applied to an embedded system. Thus, we propose a robust stereo matching system, RT-libSGM, working on the Xilinx Field-programmable gate array (FPGA) platforms. The dedicated design of each module optimizes the speed of the entire system while ensuring the flexibility of the system structure. Through an evaluation running on a Zynq FPGA board called M-KUBOS, RT-libSGM achieves state-of-the-art performance with lower power consumption. Compared with the original design (libSGM), when working on the Tegra X2 GPU, RT-libSGM runs 2 × faster at a lower energy cost.
KW - Energy efficiency
KW - Real-time
KW - Slide window
KW - Stereo Matching
KW - Vitis HLS
KW - libSGM
UR - http://www.scopus.com/inward/record.url?scp=85132389204&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85132389204&partnerID=8YFLogxK
U2 - 10.1145/3535044.3535045
DO - 10.1145/3535044.3535045
M3 - Conference contribution
AN - SCOPUS:85132389204
T3 - ACM International Conference Proceeding Series
SP - 1
EP - 9
BT - Proceedings of the 12th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2022
PB - Association for Computing Machinery
Y2 - 9 June 2022 through 10 June 2022
ER -
