Run-time power-gating techniques for low-power on-chip networks

Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Leakage power has already been consuming a considerable portion of the active power in recent process technologies. In this chapter, we survey various power gating techniques to reduce the leakage power of on-chip routers. Then we introduce a run-time fine-grained power-gating router, in which power supply to each router component (e.g., virtual-channel buffer, crossbar's multiplexer, and output latch) can be individually controlled in response to the applied workload. The fine-grained power gating router with 35 micro-power domains is designed using a commercial 65 nm process and evaluated in terms of the area overhead, application performance, and leakage power reduction.

Original languageEnglish
Title of host publicationLow Power Networks-On-Chip
PublisherSpringer
Pages21-43
Number of pages23
ISBN (Print)9781441969101
DOIs
Publication statusPublished - 2011

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Routers
Network-on-chip

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Matsutani, H., Koibuchi, M., Nakamura, H., & Amano, H. (2011). Run-time power-gating techniques for low-power on-chip networks. In Low Power Networks-On-Chip (pp. 21-43). Springer. https://doi.org/10.1007/978-1-4419-6911-8_2

Run-time power-gating techniques for low-power on-chip networks. / Matsutani, Hiroki; Koibuchi, Michihiro; Nakamura, Hiroshi; Amano, Hideharu.

Low Power Networks-On-Chip. Springer, 2011. p. 21-43.

Research output: Chapter in Book/Report/Conference proceedingChapter

Matsutani, H, Koibuchi, M, Nakamura, H & Amano, H 2011, Run-time power-gating techniques for low-power on-chip networks. in Low Power Networks-On-Chip. Springer, pp. 21-43. https://doi.org/10.1007/978-1-4419-6911-8_2
Matsutani H, Koibuchi M, Nakamura H, Amano H. Run-time power-gating techniques for low-power on-chip networks. In Low Power Networks-On-Chip. Springer. 2011. p. 21-43 https://doi.org/10.1007/978-1-4419-6911-8_2
Matsutani, Hiroki ; Koibuchi, Michihiro ; Nakamura, Hiroshi ; Amano, Hideharu. / Run-time power-gating techniques for low-power on-chip networks. Low Power Networks-On-Chip. Springer, 2011. pp. 21-43
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