Run-time power-gating techniques for low-power on-chip networks

Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Leakage power has already been consuming a considerable portion of the active power in recent process technologies. In this chapter, we survey various power gating techniques to reduce the leakage power of on-chip routers. Then we introduce a run-time fine-grained power-gating router, in which power supply to each router component (e.g., virtual-channel buffer, crossbar's multiplexer, and output latch) can be individually controlled in response to the applied workload. The fine-grained power gating router with 35 micro-power domains is designed using a commercial 65 nm process and evaluated in terms of the area overhead, application performance, and leakage power reduction.

Original languageEnglish
Title of host publicationLow Power Networks-On-Chip
PublisherSpringer
Pages21-43
Number of pages23
ISBN (Print)9781441969101
DOIs
Publication statusPublished - 2011 Dec 1

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Matsutani, H., Koibuchi, M., Nakamura, H., & Amano, H. (2011). Run-time power-gating techniques for low-power on-chip networks. In Low Power Networks-On-Chip (pp. 21-43). Springer. https://doi.org/10.1007/978-1-4419-6911-8_2