Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

E. Oki; N. Yamanaka; K. Okazaki; Y. Ohtomo

doi:10.1049/el:19990428

Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

E. Oki, N. Yamanaka, K. Okazaki, Y. Ohtomo

Research output: Contribution to journal › Article › peer-review

Abstract

A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput. 0.25 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.

Original language	English
Pages (from-to)	715-716
Number of pages	2
Journal	Electronics Letters
Volume	35
Issue number	9
DOIs	https://doi.org/10.1049/el:19990428
Publication status	Published - 1999 Apr 29
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1049/el:19990428

Cite this

@article{b5be84d30ca8454fa570f3138312861b,

title = "Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control",

abstract = "A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput. 0.25 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.",

author = "E. Oki and N. Yamanaka and K. Okazaki and Y. Ohtomo",

year = "1999",

month = apr,

day = "29",

doi = "10.1049/el:19990428",

language = "English",

volume = "35",

pages = "715--716",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "Institution of Engineering and Technology",

number = "9",

}

TY - JOUR

T1 - Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

AU - Oki, E.

AU - Yamanaka, N.

AU - Okazaki, K.

AU - Ohtomo, Y.

PY - 1999/4/29

Y1 - 1999/4/29

N2 - A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput. 0.25 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.

AB - A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput. 0.25 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.

UR - http://www.scopus.com/inward/record.url?scp=0032641525&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032641525&partnerID=8YFLogxK

U2 - 10.1049/el:19990428

DO - 10.1049/el:19990428

M3 - Article

AN - SCOPUS:0032641525

SN - 0013-5194

VL - 35

SP - 715

EP - 716

JO - Electronics Letters

JF - Electronics Letters

IS - 9

ER -

Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this