Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

E. Oki, Naoaki Yamanaka, K. Okazaki, Y. Ohtomo

Research output: Contribution to journalArticle

Abstract

A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput. 0.25 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.

Original languageEnglish
Pages (from-to)715-716
Number of pages2
JournalElectronics Letters
Volume35
Issue number9
DOIs
Publication statusPublished - 1999 Apr 29
Externally publishedYes

Fingerprint

LSI circuits
Automatic teller machines
Switches
Electric power utilization
Throughput
Oxygen

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control. / Oki, E.; Yamanaka, Naoaki; Okazaki, K.; Ohtomo, Y.

In: Electronics Letters, Vol. 35, No. 9, 29.04.1999, p. 715-716.

Research output: Contribution to journalArticle

@article{b5be84d30ca8454fa570f3138312861b,
title = "Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control",
abstract = "A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput. 0.25 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.",
author = "E. Oki and Naoaki Yamanaka and K. Okazaki and Y. Ohtomo",
year = "1999",
month = "4",
day = "29",
doi = "10.1049/el:19990428",
language = "English",
volume = "35",
pages = "715--716",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology",
number = "9",

}

TY - JOUR

T1 - Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

AU - Oki, E.

AU - Yamanaka, Naoaki

AU - Okazaki, K.

AU - Ohtomo, Y.

PY - 1999/4/29

Y1 - 1999/4/29

N2 - A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput. 0.25 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.

AB - A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput. 0.25 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.

UR - http://www.scopus.com/inward/record.url?scp=0032641525&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032641525&partnerID=8YFLogxK

U2 - 10.1049/el:19990428

DO - 10.1049/el:19990428

M3 - Article

AN - SCOPUS:0032641525

VL - 35

SP - 715

EP - 716

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 9

ER -