Scalable 10 Gbit/s 4×2 0.25 μm CMOS/SIMOX ATM switch LSI circuit based on distributed contention control

E. Oki, N. Yamanaka, K. Okazaki, Y. Ohtomo

Research output: Contribution to journalArticle

Abstract

A scalable 10 Gbit/s 4×2 ATM switch LSI circuit has been fabricated. It employs a new distributed contention control technique that makes the LSI circuit expandable. To increase the LSI circuit throughput. 0.25 μm CMOS/SIMOX (separation by implanted oxygen) technology is used. It allows the LSI circuit to offer 221 I/O pins, an operating speed of 1.25 Gbit/s and 7 W power consumption.

Original languageEnglish
Pages (from-to)715-716
Number of pages2
JournalElectronics Letters
Volume35
Issue number9
DOIs
Publication statusPublished - 1999 Apr 29

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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