Scalable deep neural network accelerator cores with cubic integration using through chip interface

Ryuichi Sakamoto; Ryo Takata; Jun Ishii; Masaaki Kondo; Hiroshi Nakamura; Tetsui Ohkubo; Takuya Kojima; Hideharu Amano

doi:10.1109/ISOCC.2017.8368843

Scalable deep neural network accelerator cores with cubic integration using through chip interface

Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embedded systems. Developing high-performance and power-efficient DNN engines becomes one of the important challenges for embedded systems. Since DNN algorithms or structures are frequently updated, flexibility and performance scalability to deal with various types of networks are crucial requirement of the DNN accelerator design. In this paper, we describe the architecture and LSI design of a flexible and scalable CNN accelerator called SNACC (Scalable Neuro Accelerator Core with Cubic integration) which consists of several processing cores, on-chip memory modules, and ThruChip Interface (TCI).

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	155-156
Number of pages	2
ISBN (Electronic)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368843
Publication status	Published - 2018 May 29
Event	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 2017 Nov 5 → 2017 Nov 8

Publication series

Name	Proceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other	14th International SoC Design Conference, ISOCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	17/11/5 → 17/11/8

Keywords

3D-Integration
Accelerator
CNN
LSI Design

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2017.8368843

Cite this

Sakamoto, R., Takata, R., Ishii, J., Kondo, M., Nakamura, H., Ohkubo, T., Kojima, T., & Amano, H. (2018). Scalable deep neural network accelerator cores with cubic integration using through chip interface. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 155-156). (Proceedings - International SoC Design Conference 2017, ISOCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368843

Scalable deep neural network accelerator cores with cubic integration using through chip interface. / Sakamoto, Ryuichi; Takata, Ryo; Ishii, Jun et al.

Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 155-156 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sakamoto, R, Takata, R, Ishii, J, Kondo, M, Nakamura, H, Ohkubo, T, Kojima, T & Amano, H 2018, Scalable deep neural network accelerator cores with cubic integration using through chip interface. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 155-156, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368843

Sakamoto R, Takata R, Ishii J, Kondo M, Nakamura H, Ohkubo T et al. Scalable deep neural network accelerator cores with cubic integration using through chip interface. In Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 155-156. (Proceedings - International SoC Design Conference 2017, ISOCC 2017). doi: 10.1109/ISOCC.2017.8368843

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AB - Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embedded systems. Developing high-performance and power-efficient DNN engines becomes one of the important challenges for embedded systems. Since DNN algorithms or structures are frequently updated, flexibility and performance scalability to deal with various types of networks are crucial requirement of the DNN accelerator design. In this paper, we describe the architecture and LSI design of a flexible and scalable CNN accelerator called SNACC (Scalable Neuro Accelerator Core with Cubic integration) which consists of several processing cores, on-chip memory modules, and ThruChip Interface (TCI).

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Scalable deep neural network accelerator cores with cubic integration using through chip interface

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Keywords

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