Scalable frame-synchronization circuit for highly parallel optical interconnections

K. Yamakoshi, R. Kawano, N. Yamanaka

Research output: Contribution to journalArticle

Abstract

A scalable frame-synchronization circuit is proposed for highly parallel high-speed optical interconnections. Its scalable architecture enables the number of channels to be increased without any decrease in the transmission rate. In HSPICE circuit simulations, a circuit using 0.25 μm CMOS technology compensated for a skew in 622 Mbit/s input data.

Original languageEnglish
Pages (from-to)2117-2118
Number of pages2
JournalElectronics Letters
Volume35
Issue number24
DOIs
Publication statusPublished - 1999 Nov 25

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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