Scalable frame-synchronization circuit for highly parallel optical interconnections

K. Yamakoshi; R. Kawano; N. Yamanaka

doi:10.1049/el:19991434

Scalable frame-synchronization circuit for highly parallel optical interconnections

K. Yamakoshi, R. Kawano, N. Yamanaka

Research output: Contribution to journal › Article › peer-review

Abstract

A scalable frame-synchronization circuit is proposed for highly parallel high-speed optical interconnections. Its scalable architecture enables the number of channels to be increased without any decrease in the transmission rate. In HSPICE circuit simulations, a circuit using 0.25 μm CMOS technology compensated for a skew in 622 Mbit/s input data.

Original language	English
Pages (from-to)	2117-2118
Number of pages	2
Journal	Electronics Letters
Volume	35
Issue number	24
DOIs	https://doi.org/10.1049/el:19991434
Publication status	Published - 1999 Nov 25
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:19991434

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title = "Scalable frame-synchronization circuit for highly parallel optical interconnections",

abstract = "A scalable frame-synchronization circuit is proposed for highly parallel high-speed optical interconnections. Its scalable architecture enables the number of channels to be increased without any decrease in the transmission rate. In HSPICE circuit simulations, a circuit using 0.25 μm CMOS technology compensated for a skew in 622 Mbit/s input data.",

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year = "1999",

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AB - A scalable frame-synchronization circuit is proposed for highly parallel high-speed optical interconnections. Its scalable architecture enables the number of channels to be increased without any decrease in the transmission rate. In HSPICE circuit simulations, a circuit using 0.25 μm CMOS technology compensated for a skew in 622 Mbit/s input data.

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Scalable frame-synchronization circuit for highly parallel optical interconnections

Abstract

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