A scalable frame-synchronization circuit is proposed for highly parallel high-speed optical interconnections. Its scalable architecture enables the number of channels to be increased without any decrease in the transmission rate. In HSPICE circuit simulations, a circuit using 0.25 μm CMOS technology compensated for a skew in 622 Mbit/s input data.
|Number of pages||2|
|Publication status||Published - 1999 Nov 25|
ASJC Scopus subject areas
- Electrical and Electronic Engineering