Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

As the number of cores on a chip increases, Networks-on-Chip (NoCs) that connect many cores would face long links to reduce hop counts. The long links become bottlenecks in terms of both energy and RC delays as technology advances. To alleviate the negative impact of long links, we propose decentralized routers for NoCs. A decentralized router consists of multiple submodules that are positioned on a link, and hence the long links are segmented. Furthermore, we illustrate the design of an entire network that uses decentralized routers to obtain a good tradeoff between hop counts and wire delays per hop. Decentralized routers are effective especially in high-radix topologies, such as the flattened butterfly, and energy-delay product is reduced by greater than 60 percent. As NoCs become larger and more complex, the benefit of the decentralized routers will become more significant.

Original languageEnglish
Article number7562562
Pages (from-to)702-716
Number of pages15
JournalIEEE Transactions on Computers
Volume66
Issue number4
DOIs
Publication statusPublished - 2017 Apr 1

Fingerprint

Router
Routers
Decentralized
Count
Many-core
Energy
Percent
Chip
Trade-offs
Topology
Network on chip
Network-on-chip
Entire
Wire

Keywords

  • Interconnection networks
  • network topology
  • networks-on-chip
  • router architecture

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Software
  • Hardware and Architecture
  • Computational Theory and Mathematics

Cite this

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. / Yasudo, Ryota; Matsutani, Hiroki; Koibuchi, Michihiro; Amano, Hideharu; Nakamura, Tadao.

In: IEEE Transactions on Computers, Vol. 66, No. 4, 7562562, 01.04.2017, p. 702-716.

Research output: Contribution to journalArticle

Yasudo, Ryota ; Matsutani, Hiroki ; Koibuchi, Michihiro ; Amano, Hideharu ; Nakamura, Tadao. / Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. In: IEEE Transactions on Computers. 2017 ; Vol. 66, No. 4. pp. 702-716.
@article{ad800410bafe45aea02bcc56712f0524,
title = "Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers",
abstract = "As the number of cores on a chip increases, Networks-on-Chip (NoCs) that connect many cores would face long links to reduce hop counts. The long links become bottlenecks in terms of both energy and RC delays as technology advances. To alleviate the negative impact of long links, we propose decentralized routers for NoCs. A decentralized router consists of multiple submodules that are positioned on a link, and hence the long links are segmented. Furthermore, we illustrate the design of an entire network that uses decentralized routers to obtain a good tradeoff between hop counts and wire delays per hop. Decentralized routers are effective especially in high-radix topologies, such as the flattened butterfly, and energy-delay product is reduced by greater than 60 percent. As NoCs become larger and more complex, the benefit of the decentralized routers will become more significant.",
keywords = "Interconnection networks, network topology, networks-on-chip, router architecture",
author = "Ryota Yasudo and Hiroki Matsutani and Michihiro Koibuchi and Hideharu Amano and Tadao Nakamura",
year = "2017",
month = "4",
day = "1",
doi = "10.1109/TC.2016.2606597",
language = "English",
volume = "66",
pages = "702--716",
journal = "IEEE Transactions on Computers",
issn = "0018-9340",
publisher = "IEEE Computer Society",
number = "4",

}

TY - JOUR

T1 - Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

AU - Yasudo, Ryota

AU - Matsutani, Hiroki

AU - Koibuchi, Michihiro

AU - Amano, Hideharu

AU - Nakamura, Tadao

PY - 2017/4/1

Y1 - 2017/4/1

N2 - As the number of cores on a chip increases, Networks-on-Chip (NoCs) that connect many cores would face long links to reduce hop counts. The long links become bottlenecks in terms of both energy and RC delays as technology advances. To alleviate the negative impact of long links, we propose decentralized routers for NoCs. A decentralized router consists of multiple submodules that are positioned on a link, and hence the long links are segmented. Furthermore, we illustrate the design of an entire network that uses decentralized routers to obtain a good tradeoff between hop counts and wire delays per hop. Decentralized routers are effective especially in high-radix topologies, such as the flattened butterfly, and energy-delay product is reduced by greater than 60 percent. As NoCs become larger and more complex, the benefit of the decentralized routers will become more significant.

AB - As the number of cores on a chip increases, Networks-on-Chip (NoCs) that connect many cores would face long links to reduce hop counts. The long links become bottlenecks in terms of both energy and RC delays as technology advances. To alleviate the negative impact of long links, we propose decentralized routers for NoCs. A decentralized router consists of multiple submodules that are positioned on a link, and hence the long links are segmented. Furthermore, we illustrate the design of an entire network that uses decentralized routers to obtain a good tradeoff between hop counts and wire delays per hop. Decentralized routers are effective especially in high-radix topologies, such as the flattened butterfly, and energy-delay product is reduced by greater than 60 percent. As NoCs become larger and more complex, the benefit of the decentralized routers will become more significant.

KW - Interconnection networks

KW - network topology

KW - networks-on-chip

KW - router architecture

UR - http://www.scopus.com/inward/record.url?scp=85027335590&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85027335590&partnerID=8YFLogxK

U2 - 10.1109/TC.2016.2606597

DO - 10.1109/TC.2016.2606597

M3 - Article

AN - SCOPUS:85027335590

VL - 66

SP - 702

EP - 716

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 4

M1 - 7562562

ER -