Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

As the number of cores on a chip increases, Networks-on-Chip (NoCs) that connect many cores would face long links to reduce hop counts. The long links become bottlenecks in terms of both energy and RC delays as technology advances. To alleviate the negative impact of long links, we propose decentralized routers for NoCs. A decentralized router consists of multiple submodules that are positioned on a link, and hence the long links are segmented. Furthermore, we illustrate the design of an entire network that uses decentralized routers to obtain a good tradeoff between hop counts and wire delays per hop. Decentralized routers are effective especially in high-radix topologies, such as the flattened butterfly, and energy-delay product is reduced by greater than 60 percent. As NoCs become larger and more complex, the benefit of the decentralized routers will become more significant.

Original languageEnglish
Article number7562562
Pages (from-to)702-716
Number of pages15
JournalIEEE Transactions on Computers
Volume66
Issue number4
DOIs
Publication statusPublished - 2017 Apr 1

Keywords

  • Interconnection networks
  • network topology
  • networks-on-chip
  • router architecture

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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