Scenario for catastrophic failure in interconnect structures under chip package interaction

Masaki Omiya, Shoji Kamiya, Nobuyuki Shishido, Kozo Koiwa, Hisashi Sato, Masahiro Nishida, Takashi Suzuki, Tomoji Nakamura, Toshiaki Suzuki, Takeshi Nokuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes the critical importance of interfacial strength between copper lines and cap layer for catastrophic failure due to chip-package interaction (CPI). Recently, copper interconnects and insulating layers are stacked alternately in semiconductor devices. Especially, copper/low-k structures are widely selected. However, the low-k materials have weak mechanical properties, which sometimes induces reliability issues, especially, chip package interactions. In our previous works, the interfacial strength of Cu/Cap has been successfully measured on the sub-micron scale. In this paper, based on the measured results, we try to simulate the initiation and propagation of failure in interconnect structures and discuss the scenario for catastrophic failure under CPI.

Original languageEnglish
Title of host publicationIEEE International Reliability Physics Symposium Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages5C31-5C35
Volume2015-May
ISBN (Print)9781467373623
DOIs
Publication statusPublished - 2015 May 26
EventIEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States
Duration: 2015 Apr 192015 Apr 23

Other

OtherIEEE International Reliability Physics Symposium, IRPS 2015
CountryUnited States
CityMonterey
Period15/4/1915/4/23

Keywords

  • chip-package interaction
  • copper line
  • crack
  • interfacial strength
  • low-k
  • numerical simulation

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'Scenario for catastrophic failure in interconnect structures under chip package interaction'. Together they form a unique fingerprint.

  • Cite this

    Omiya, M., Kamiya, S., Shishido, N., Koiwa, K., Sato, H., Nishida, M., Suzuki, T., Nakamura, T., Suzuki, T., & Nokuo, T. (2015). Scenario for catastrophic failure in interconnect structures under chip package interaction. In IEEE International Reliability Physics Symposium Proceedings (Vol. 2015-May, pp. 5C31-5C35). [7112751] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS.2015.7112751