Scenario for catastrophic failure in interconnect structures under chip package interaction

Masaki Omiya; Shoji Kamiya; Nobuyuki Shishido; Kozo Koiwa; Hisashi Sato; Masahiro Nishida; Takashi Suzuki; Tomoji Nakamura; Toshiaki Suzuki; Takeshi Nokuo

doi:10.1109/IRPS.2015.7112751

Scenario for catastrophic failure in interconnect structures under chip package interaction

Masaki Omiya, Shoji Kamiya, Nobuyuki Shishido, Kozo Koiwa, Hisashi Sato, Masahiro Nishida, Takashi Suzuki, Tomoji Nakamura, Toshiaki Suzuki, Takeshi Nokuo

Department of Mechanical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper describes the critical importance of interfacial strength between copper lines and cap layer for catastrophic failure due to chip-package interaction (CPI). Recently, copper interconnects and insulating layers are stacked alternately in semiconductor devices. Especially, copper/low-k structures are widely selected. However, the low-k materials have weak mechanical properties, which sometimes induces reliability issues, especially, chip package interactions. In our previous works, the interfacial strength of Cu/Cap has been successfully measured on the sub-micron scale. In this paper, based on the measured results, we try to simulate the initiation and propagation of failure in interconnect structures and discuss the scenario for catastrophic failure under CPI.

Original language	English
Title of host publication	IEEE International Reliability Physics Symposium Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	5C31-5C35
Volume	2015-May
ISBN (Print)	9781467373623
DOIs	https://doi.org/10.1109/IRPS.2015.7112751
Publication status	Published - 2015 May 26
Event	IEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States Duration: 2015 Apr 19 → 2015 Apr 23

Other

Other	IEEE International Reliability Physics Symposium, IRPS 2015
Country	United States
City	Monterey
Period	15/4/19 → 15/4/23

Keywords

chip-package interaction
copper line
crack
interfacial strength
low-k
numerical simulation

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/IRPS.2015.7112751

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Omiya, M., Kamiya, S., Shishido, N., Koiwa, K., Sato, H., Nishida, M., Suzuki, T., Nakamura, T., Suzuki, T., & Nokuo, T. (2015). Scenario for catastrophic failure in interconnect structures under chip package interaction. In IEEE International Reliability Physics Symposium Proceedings (Vol. 2015-May, pp. 5C31-5C35). [7112751] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS.2015.7112751

Scenario for catastrophic failure in interconnect structures under chip package interaction. / Omiya, Masaki; Kamiya, Shoji; Shishido, Nobuyuki; Koiwa, Kozo; Sato, Hisashi; Nishida, Masahiro; Suzuki, Takashi; Nakamura, Tomoji; Suzuki, Toshiaki; Nokuo, Takeshi.

IEEE International Reliability Physics Symposium Proceedings. Vol. 2015-May Institute of Electrical and Electronics Engineers Inc., 2015. p. 5C31-5C35 7112751.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Omiya, M, Kamiya, S, Shishido, N, Koiwa, K, Sato, H, Nishida, M, Suzuki, T, Nakamura, T, Suzuki, T & Nokuo, T 2015, Scenario for catastrophic failure in interconnect structures under chip package interaction. in IEEE International Reliability Physics Symposium Proceedings. vol. 2015-May, 7112751, Institute of Electrical and Electronics Engineers Inc., pp. 5C31-5C35, IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, United States, 15/4/19. https://doi.org/10.1109/IRPS.2015.7112751

Omiya, Masaki ; Kamiya, Shoji ; Shishido, Nobuyuki ; Koiwa, Kozo ; Sato, Hisashi ; Nishida, Masahiro ; Suzuki, Takashi ; Nakamura, Tomoji ; Suzuki, Toshiaki ; Nokuo, Takeshi. / Scenario for catastrophic failure in interconnect structures under chip package interaction. IEEE International Reliability Physics Symposium Proceedings. Vol. 2015-May Institute of Electrical and Electronics Engineers Inc., 2015. pp. 5C31-5C35

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abstract = "This paper describes the critical importance of interfacial strength between copper lines and cap layer for catastrophic failure due to chip-package interaction (CPI). Recently, copper interconnects and insulating layers are stacked alternately in semiconductor devices. Especially, copper/low-k structures are widely selected. However, the low-k materials have weak mechanical properties, which sometimes induces reliability issues, especially, chip package interactions. In our previous works, the interfacial strength of Cu/Cap has been successfully measured on the sub-micron scale. In this paper, based on the measured results, we try to simulate the initiation and propagation of failure in interconnect structures and discuss the scenario for catastrophic failure under CPI.",

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