Abstract
This paper describes the critical importance of interfacial strength between copper lines and cap layer for catastrophic failure due to chip-package interaction (CPI). Recently, copper interconnects and insulating layers are stacked alternately in semiconductor devices. Especially, copper/low-k structures are widely selected. However, the low-k materials have weak mechanical properties, which sometimes induces reliability issues, especially, chip package interactions. In our previous works, the interfacial strength of Cu/Cap has been successfully measured on the sub-micron scale. In this paper, based on the measured results, we try to simulate the initiation and propagation of failure in interconnect structures and discuss the scenario for catastrophic failure under CPI.
Original language | English |
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Title of host publication | IEEE International Reliability Physics Symposium Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 5C31-5C35 |
Volume | 2015-May |
ISBN (Print) | 9781467373623 |
DOIs | |
Publication status | Published - 2015 May 26 |
Event | IEEE International Reliability Physics Symposium, IRPS 2015 - Monterey, United States Duration: 2015 Apr 19 → 2015 Apr 23 |
Other
Other | IEEE International Reliability Physics Symposium, IRPS 2015 |
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Country | United States |
City | Monterey |
Period | 15/4/19 → 15/4/23 |
Keywords
- chip-package interaction
- copper line
- crack
- interfacial strength
- low-k
- numerical simulation
ASJC Scopus subject areas
- Engineering(all)