Scheduling algorithm with priority of active buffer for variable-length IP packet over input-buffered ATM switch

In the input buffered ATM (Asynchronous Transfer Mode) switches, HoL (Head of Line) blocking can be eliminated entirely by VOQ(Virtual Output Queuing), in which each input port maintains a separate buffer for each output port. On the other hand, recently IP (Internet Protocol) traffic has increased explosively, therefore to manage IP packets over ATM, IP-PIM(IP - Parallel Iterative Matching) has been proposed. However, queue length of other buffers increases with IP-PIM, since cells of same packet are switched consecutively. Therefore, IP-PIM causes degradation of packet loss probability. In this paper, by defining the buffer at which cells that belong to packet arrive in a certain time slot as active buffer, we propose a new scheduling algorithm that gives priority to active buffer so that cells which belong to packets can be switched effectively without increasing queue length. We evaluate the packet loss probability and the mean packet delay in computer simulations. As a result, it is shown that the proposed scheme can improve the packet loss probability with negligible degradation of the mean packet delay.