Scheduling algorithm with priority of active buffer for variable-length IP packet over input-buffered ATM switch

Y. Nakaki, K. Okazaki, K. Sakamoto, Y. Nishino, Iwao Sasase

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In the input buffered ATM (Asynchronous Transfer Mode) switches, HoL (Head of Line) blocking can be eliminated entirely by VOQ(Virtual Output Queuing), in which each input port maintains a separate buffer for each output port. On the other hand, recently IP (Internet Protocol) traffic has increased explosively, therefore to manage IP packets over ATM, IP-PIM(IP - Parallel Iterative Matching) has been proposed. However, queue length of other buffers increases with IP-PIM, since cells of same packet are switched consecutively. Therefore, IP-PIM causes degradation of packet loss probability. In this paper, by defining the buffer at which cells that belong to packet arrive in a certain time slot as active buffer, we propose a new scheduling algorithm that gives priority to active buffer so that cells which belong to packets can be switched effectively without increasing queue length. We evaluate the packet loss probability and the mean packet delay in computer simulations. As a result, it is shown that the proposed scheme can improve the packet loss probability with negligible degradation of the mean packet delay.

Original languageEnglish
Title of host publicationIEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings
Pages526-529
Number of pages4
VolumeII
Publication statusPublished - 2001
Event2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 2001) - Victoria, BC, Canada
Duration: 2001 Aug 262001 Aug 28

Other

Other2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 2001)
CountryCanada
CityVictoria, BC
Period01/8/2601/8/28

Fingerprint

Internet protocols
Asynchronous transfer mode
Scheduling algorithms
Switches
Packet loss
Degradation
Computer simulation

ASJC Scopus subject areas

  • Signal Processing

Cite this

Nakaki, Y., Okazaki, K., Sakamoto, K., Nishino, Y., & Sasase, I. (2001). Scheduling algorithm with priority of active buffer for variable-length IP packet over input-buffered ATM switch. In IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings (Vol. II, pp. 526-529)

Scheduling algorithm with priority of active buffer for variable-length IP packet over input-buffered ATM switch. / Nakaki, Y.; Okazaki, K.; Sakamoto, K.; Nishino, Y.; Sasase, Iwao.

IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings. Vol. II 2001. p. 526-529.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakaki, Y, Okazaki, K, Sakamoto, K, Nishino, Y & Sasase, I 2001, Scheduling algorithm with priority of active buffer for variable-length IP packet over input-buffered ATM switch. in IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings. vol. II, pp. 526-529, 2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 2001), Victoria, BC, Canada, 01/8/26.
Nakaki Y, Okazaki K, Sakamoto K, Nishino Y, Sasase I. Scheduling algorithm with priority of active buffer for variable-length IP packet over input-buffered ATM switch. In IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings. Vol. II. 2001. p. 526-529
Nakaki, Y. ; Okazaki, K. ; Sakamoto, K. ; Nishino, Y. ; Sasase, Iwao. / Scheduling algorithm with priority of active buffer for variable-length IP packet over input-buffered ATM switch. IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings. Vol. II 2001. pp. 526-529
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