Shared vs. Snoop: Evaluation of cache structure for single-chip multiprocessors

Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, Keisuke Inoue, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that 1-port large shared cache achieves the best performance if there is no delay penalty for arbitration and accessing the bus. However, if 1-clock delay is assumed for accessing the shared cache, a snoop cache with internal wide bus and invalidate style NewKeio protocol overcomes shared caches.

Original languageEnglish
Title of host publicationEuro-Par 1997 Parallel Processing - Third International Conference, Proceedings
Pages793-797
Number of pages5
Publication statusPublished - 1997 Dec 1
Event3rd International Conference on Parallel Processing, Euro-Par 1997 - Passau, Germany
Duration: 1997 Aug 261997 Aug 29

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume1300 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other3rd International Conference on Parallel Processing, Euro-Par 1997
CountryGermany
CityPassau
Period97/8/2697/8/29

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ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

Cite this

Kisuki, T., Wakabayashi, M., Yamamoto, J., Inoue, K., & Amano, H. (1997). Shared vs. Snoop: Evaluation of cache structure for single-chip multiprocessors. In Euro-Par 1997 Parallel Processing - Third International Conference, Proceedings (pp. 793-797). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1300 LNCS).