We successfully reduced the parasitic resistance of nanowire transistors (NW Tr.) by raised S/D extensions with thin spacers (<10nm). Id variations are suppressed by spacer thinning and parasitic capacitance increase is minimal. By adopting <100> NW instead of <110> NW, Ion = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Long-L mobility (μ) was systematically studied by separating top and side channel μ. μ of <100> nFETs and <110> pFETs (potentially-high ?) largely degrade due to side-surface roughness. Gate stress and interface traps affect μ?of <110> nFETs and <110> pFETs, respectively.