Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions

M. Saitoh, Y. Nakabayashi, H. Itokawa, M. Murano, I. Mizushima, Ken Uchida, T. Numata

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Abstract

We successfully reduced the parasitic resistance of nanowire transistors (NW Tr.) by raised S/D extensions with thin spacers (<10nm). Id variations are suppressed by spacer thinning and parasitic capacitance increase is minimal. By adopting <100> NW instead of <110> NW, Ion = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Long-L mobility (μ) was systematically studied by separating top and side channel μ. μ of <100> nFETs and <110> pFETs (potentially-high ?) largely degrade due to side-surface roughness. Gate stress and interface traps affect μ?of <110> nFETs and <110> pFETs, respectively.

Original languageEnglish
Title of host publicationDigest of Technical Papers - Symposium on VLSI Technology
Pages169-170
Number of pages2
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States
Duration: 2010 Jun 152010 Jun 17

Other

Other2010 Symposium on VLSI Technology, VLSIT 2010
CountryUnited States
CityHonolulu, HI
Period10/6/1510/6/17

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Nanowires
Transistors
Surface roughness
Ions

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Saitoh, M., Nakabayashi, Y., Itokawa, H., Murano, M., Mizushima, I., Uchida, K., & Numata, T. (2010). Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions. In Digest of Technical Papers - Symposium on VLSI Technology (pp. 169-170). [5556214] https://doi.org/10.1109/VLSIT.2010.5556214

Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions. / Saitoh, M.; Nakabayashi, Y.; Itokawa, H.; Murano, M.; Mizushima, I.; Uchida, Ken; Numata, T.

Digest of Technical Papers - Symposium on VLSI Technology. 2010. p. 169-170 5556214.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Saitoh, M, Nakabayashi, Y, Itokawa, H, Murano, M, Mizushima, I, Uchida, K & Numata, T 2010, Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions. in Digest of Technical Papers - Symposium on VLSI Technology., 5556214, pp. 169-170, 2010 Symposium on VLSI Technology, VLSIT 2010, Honolulu, HI, United States, 10/6/15. https://doi.org/10.1109/VLSIT.2010.5556214
Saitoh M, Nakabayashi Y, Itokawa H, Murano M, Mizushima I, Uchida K et al. Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions. In Digest of Technical Papers - Symposium on VLSI Technology. 2010. p. 169-170. 5556214 https://doi.org/10.1109/VLSIT.2010.5556214
Saitoh, M. ; Nakabayashi, Y. ; Itokawa, H. ; Murano, M. ; Mizushima, I. ; Uchida, Ken ; Numata, T. / Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions. Digest of Technical Papers - Symposium on VLSI Technology. 2010. pp. 169-170
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