Abstract
We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width WNW down to 10 nm. We found that the parasitic resistance RSD of nanowire transistors is dominated by nanowire-shaped source/drain (S/D) regions under the gate spacer whose resistivity is higher than that in wider regions. We succeeded in significant RSD reduction by raised S/D with thin gate spacer whose width is 10 nm. Although the parasitic capacitance Cpara increases by spacer thinning, Cpara increase is much smaller than RSD reduction, and great performance improvement is obtained for a WNW of less than 15 nm.
Original language | English |
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Article number | 5701650 |
Pages (from-to) | 273-275 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 32 |
Issue number | 3 |
DOIs | |
Publication status | Published - 2011 Mar 1 |
Keywords
- Drain-induced barrier lowering (DIBL)
- nanowire transistor
- parasitic capacitance
- parasitic resistance
- raised source/drain (S/D)
- trigate
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering