Abstract
We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width WNW down to 10 nm. We found that the parasitic resistance RSD of nanowire transistors is dominated by nanowire-shaped source/drain (S/D) regions under the gate spacer whose resistivity is higher than that in wider regions. We succeeded in significant RSD reduction by raised S/D with thin gate spacer whose width is 10 nm. Although the parasitic capacitance Cpara increases by spacer thinning, Cpara increase is much smaller than RSD reduction, and great performance improvement is obtained for a WNW of less than 15 nm.
| Original language | English |
|---|---|
| Article number | 5701650 |
| Pages (from-to) | 273-275 |
| Number of pages | 3 |
| Journal | IEEE Electron Device Letters |
| Volume | 32 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2011 Mar |
| Externally published | Yes |
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Keywords
- Drain-induced barrier lowering (DIBL)
- nanowire transistor
- parasitic capacitance
- parasitic resistance
- raised source/drain (S/D)
- trigate
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
Short-channel performance improvement by raised source/drain extensions with thin spacers in trigate silicon nanowire MOSFETs. / Saitoh, Masumi; Nakabayashi, Yukio; Uchida, Ken; Numata, Toshinori.
In: IEEE Electron Device Letters, Vol. 32, No. 3, 5701650, 03.2011, p. 273-275.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Short-channel performance improvement by raised source/drain extensions with thin spacers in trigate silicon nanowire MOSFETs
AU - Saitoh, Masumi
AU - Nakabayashi, Yukio
AU - Uchida, Ken
AU - Numata, Toshinori
PY - 2011/3
Y1 - 2011/3
N2 - We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width WNW down to 10 nm. We found that the parasitic resistance RSD of nanowire transistors is dominated by nanowire-shaped source/drain (S/D) regions under the gate spacer whose resistivity is higher than that in wider regions. We succeeded in significant RSD reduction by raised S/D with thin gate spacer whose width is 10 nm. Although the parasitic capacitance Cpara increases by spacer thinning, Cpara increase is much smaller than RSD reduction, and great performance improvement is obtained for a WNW of less than 15 nm.
AB - We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width WNW down to 10 nm. We found that the parasitic resistance RSD of nanowire transistors is dominated by nanowire-shaped source/drain (S/D) regions under the gate spacer whose resistivity is higher than that in wider regions. We succeeded in significant RSD reduction by raised S/D with thin gate spacer whose width is 10 nm. Although the parasitic capacitance Cpara increases by spacer thinning, Cpara increase is much smaller than RSD reduction, and great performance improvement is obtained for a WNW of less than 15 nm.
KW - Drain-induced barrier lowering (DIBL)
KW - nanowire transistor
KW - parasitic capacitance
KW - parasitic resistance
KW - raised source/drain (S/D)
KW - trigate
UR - http://www.scopus.com/inward/record.url?scp=79951958788&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79951958788&partnerID=8YFLogxK
U2 - 10.1109/LED.2010.2101043
DO - 10.1109/LED.2010.2101043
M3 - Article
AN - SCOPUS:79951958788
VL - 32
SP - 273
EP - 275
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
SN - 0741-3106
IS - 3
M1 - 5701650
ER -