Short-channel performance improvement by raised source/drain extensions with thin spacers in trigate silicon nanowire MOSFETs

Masumi Saitoh; Yukio Nakabayashi; Ken Uchida; Toshinori Numata

doi:10.1109/LED.2010.2101043

Short-channel performance improvement by raised source/drain extensions with thin spacers in trigate silicon nanowire MOSFETs

Masumi Saitoh, Yukio Nakabayashi, Ken Uchida, Toshinori Numata

Research output: Contribution to journal › Article

32 Citations (Scopus)

Abstract

We investigate the short-channel performance of trigate silicon nanowire transistors. Drain-induced barrier lowering at a gate length of 25 nm is strongly suppressed by reducing the nanowire width W_NW down to 10 nm. We found that the parasitic resistance R_SD of nanowire transistors is dominated by nanowire-shaped source/drain (S/D) regions under the gate spacer whose resistivity is higher than that in wider regions. We succeeded in significant R_SD reduction by raised S/D with thin gate spacer whose width is 10 nm. Although the parasitic capacitance C_para increases by spacer thinning, C_para increase is much smaller than R_SD reduction, and great performance improvement is obtained for a W_NW of less than 15 nm.

Original language	English
Article number	5701650
Pages (from-to)	273-275
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	32
Issue number	3
DOIs	https://doi.org/10.1109/LED.2010.2101043
Publication status	Published - 2011 Mar 1

Keywords

Drain-induced barrier lowering (DIBL)
nanowire transistor
parasitic capacitance
parasitic resistance
raised source/drain (S/D)
trigate

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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Saitoh, M., Nakabayashi, Y., Uchida, K., & Numata, T. (2011). Short-channel performance improvement by raised source/drain extensions with thin spacers in trigate silicon nanowire MOSFETs. IEEE Electron Device Letters, 32(3), 273-275. [5701650]. https://doi.org/10.1109/LED.2010.2101043

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