Si nanodevices for random number generating circuits for cryptographic security

S. Fujita; K. Uchida; S. Yasuda; R. Ohba; H. Nozaki; T. Tanamoto

Si nanodevices for random number generating circuits for cryptographic security

S. Fujita, K. Uchida, S. Yasuda, R. Ohba, H. Nozaki, T. Tanamoto

Research output: Contribution to journal › Conference article › peer-review

Abstract

Small random-number-generating circuits for cryptographic security using Si nano-devices are described. The basis of these circuits is that nano-devices hold random electrical properties naturally that were previously regarded as a negative feature. Results of statistical tests indicate that these circuits generate extremely high-quality random numbers with relatively few transistors.

Original language	English
Pages (from-to)	238-239+550
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	47
Publication status	Published - 2003 Dec 1
Event	Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement - San Francisco, CA., United States Duration: 2003 Feb 15 → 2003 Feb 19

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "Si nanodevices for random number generating circuits for cryptographic security",

abstract = "Small random-number-generating circuits for cryptographic security using Si nano-devices are described. The basis of these circuits is that nano-devices hold random electrical properties naturally that were previously regarded as a negative feature. Results of statistical tests indicate that these circuits generate extremely high-quality random numbers with relatively few transistors.",

author = "S. Fujita and K. Uchida and S. Yasuda and R. Ohba and H. Nozaki and T. Tanamoto",

year = "2003",

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AU - Fujita, S.

AU - Uchida, K.

AU - Yasuda, S.

AU - Ohba, R.

AU - Nozaki, H.

AU - Tanamoto, T.

PY - 2003/12/1

Y1 - 2003/12/1

N2 - Small random-number-generating circuits for cryptographic security using Si nano-devices are described. The basis of these circuits is that nano-devices hold random electrical properties naturally that were previously regarded as a negative feature. Results of statistical tests indicate that these circuits generate extremely high-quality random numbers with relatively few transistors.

AB - Small random-number-generating circuits for cryptographic security using Si nano-devices are described. The basis of these circuits is that nano-devices hold random electrical properties naturally that were previously regarded as a negative feature. Results of statistical tests indicate that these circuits generate extremely high-quality random numbers with relatively few transistors.

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JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement

Y2 - 15 February 2003 through 19 February 2003

ER -

Si nanodevices for random number generating circuits for cryptographic security

Abstract

ASJC Scopus subject areas

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