Si nanodevices for random number generating circuits for cryptographic security

S. Fujita, Ken Uchida, S. Yasuda, R. Ohba, H. Nozaki, T. Tanamoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Small random-number-generating circuits for cryptographic security using Si nano-devices are described. The basis of these circuits is that nano-devices hold random electrical properties naturally that were previously regarded as a negative feature. Results of statistical tests indicate that these circuits generate extremely high-quality random numbers with relatively few transistors.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
EditorsL.C. Fujino, M. Amiri, A. Grabel, D. Jaeger, K.C. Smith
Pages238-239+550
Volume47
Publication statusPublished - 2003
Externally publishedYes
EventDigest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement - San Francisco, CA., United States
Duration: 2003 Feb 152003 Feb 19

Other

OtherDigest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement
CountryUnited States
CitySan Francisco, CA.
Period03/2/1503/2/19

Fingerprint

Networks (circuits)
Statistical tests
Transistors
Electric properties

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Fujita, S., Uchida, K., Yasuda, S., Ohba, R., Nozaki, H., & Tanamoto, T. (2003). Si nanodevices for random number generating circuits for cryptographic security. In L. C. Fujino, M. Amiri, A. Grabel, D. Jaeger, & K. C. Smith (Eds.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 47, pp. 238-239+550)

Si nanodevices for random number generating circuits for cryptographic security. / Fujita, S.; Uchida, Ken; Yasuda, S.; Ohba, R.; Nozaki, H.; Tanamoto, T.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. ed. / L.C. Fujino; M. Amiri; A. Grabel; D. Jaeger; K.C. Smith. Vol. 47 2003. p. 238-239+550.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fujita, S, Uchida, K, Yasuda, S, Ohba, R, Nozaki, H & Tanamoto, T 2003, Si nanodevices for random number generating circuits for cryptographic security. in LC Fujino, M Amiri, A Grabel, D Jaeger & KC Smith (eds), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 47, pp. 238-239+550, Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement, San Francisco, CA., United States, 03/2/15.
Fujita S, Uchida K, Yasuda S, Ohba R, Nozaki H, Tanamoto T. Si nanodevices for random number generating circuits for cryptographic security. In Fujino LC, Amiri M, Grabel A, Jaeger D, Smith KC, editors, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 47. 2003. p. 238-239+550
Fujita, S. ; Uchida, Ken ; Yasuda, S. ; Ohba, R. ; Nozaki, H. ; Tanamoto, T. / Si nanodevices for random number generating circuits for cryptographic security. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. editor / L.C. Fujino ; M. Amiri ; A. Grabel ; D. Jaeger ; K.C. Smith. Vol. 47 2003. pp. 238-239+550
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