Signal transmission and coding architecture for next-generation ethernet

Hidehiro Toyoda, Hiroaki Nishi, Shinji Nishimura, Hisaaki Kanai, Katsuyoshi Harasawa

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)

Abstract

The first practical approach to 100-Gigabit Ethernet, i.e., Ethernet with a throughput of 100-Gb/s, is proposed for use in the next generation of LANs for GRID computing and large-capacity data centers. New structures, including a coding architecture, de-skewing method and high-speed packaging techniques, are introduced to the PHY layer to obtain the required data rate. Our form of 100-Gigabit Ethernet uses 10-Gb/s x 10-channel CWDM or parallel-optical links. The coding architecture is formed of 64B/66B codes, modified for the CWDM and parallel links. In the de-skewing of the parallel signals, specially designed IDLE characters are used to compensate for skewing of data in the respective signal lanes. Advanced packaging techniques, which suppress the propagation loss and reflection of the 10-Gb/s lanes to obtain high-speed, good integrity and low-noise signaling, are proposed and evaluated. The proposed architectural features make this 100-Gigabit Ethernet concept practical for next-generation LANs.

Original languageEnglish
Pages (from-to)2317-2324
Number of pages8
JournalIEICE Transactions on Information and Systems
VolumeE86-D
Issue number11
Publication statusPublished - 2003 Nov

Keywords

  • 100-gigabit ethernet
  • 64B/66B
  • Skew compensation

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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