Silicon nano-crystals based MOS memory and effects of traps on charge storage characteristics

Y. Shi, S. L. Gu, X. L. Yuan, Y. D. Zheng, K. Saito, H. Ishikuro, T. Hiramoto

Research output: Contribution to conferencePaper

8 Citations (Scopus)

Abstract

MOS memory device with silicon nano-crystals based floating gate on very narrow channel has been fabricated. Large threshold voltage shifts of up to 1 V are obtained by applying small electric field to the tunneling oxide for write/erase operation. Furthermore, charge storage characteristics have been investigated in the MOS diodes, where various interface traps and defects were introduced by thermal annealing treatment.

Original languageEnglish
Pages838-841
Number of pages4
Publication statusPublished - 1998 Dec 1
Externally publishedYes
EventProceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China
Duration: 1998 Oct 211998 Oct 23

Other

OtherProceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology
CityBeijing, China
Period98/10/2198/10/23

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Shi, Y., Gu, S. L., Yuan, X. L., Zheng, Y. D., Saito, K., Ishikuro, H., & Hiramoto, T. (1998). Silicon nano-crystals based MOS memory and effects of traps on charge storage characteristics. 838-841. Paper presented at Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology, Beijing, China, .