Skywalk: A topology for HPC networks with low-delay switches

Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

With low-delay switches on the horizon, end-to-end latency in large-scale High Performance Computing (HPC) interconnects will be dominated by cable delays. In this context we define a new network topology, Skywalk, for deploying low-latency interconnects in upcoming HPC systems. Skywalk uses randomness to achieve low latency, but does so in a way that accounts for the physical layout of the topology so as to lead to further cable length and thus latency reductions. Via graph analysis and discrete-event simulation we show that Skywalk compares favorably (in terms of latency, cable length, and throughput) to traditional low-degree torus and moderate-degree hypercube topologies, to high-degree fully-connected Dragonfly topologies, to the HyperX topology, and to recently proposed fully random topologies.

Original languageEnglish
Title of host publicationProceedings of the International Parallel and Distributed Processing Symposium, IPDPS
PublisherIEEE Computer Society
Pages263-272
Number of pages10
ISBN (Print)9780769552071
DOIs
Publication statusPublished - 2014
Event28th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2014 - Phoenix, AZ, United States
Duration: 2014 May 192014 May 23

Other

Other28th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2014
CountryUnited States
CityPhoenix, AZ
Period14/5/1914/5/23

Fingerprint

Switches
Topology
Cables
Discrete event simulation
Throughput

Keywords

  • cabinet layout
  • high performance computing
  • Interconnection network
  • network topology

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Hardware and Architecture
  • Software

Cite this

Fujiwara, I., Koibuchi, M., Matsutani, H., & Casanova, H. (2014). Skywalk: A topology for HPC networks with low-delay switches. In Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS (pp. 263-272). [6877261] IEEE Computer Society. https://doi.org/10.1109/IPDPS.2014.37

Skywalk : A topology for HPC networks with low-delay switches. / Fujiwara, Ikki; Koibuchi, Michihiro; Matsutani, Hiroki; Casanova, Henri.

Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS. IEEE Computer Society, 2014. p. 263-272 6877261.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fujiwara, I, Koibuchi, M, Matsutani, H & Casanova, H 2014, Skywalk: A topology for HPC networks with low-delay switches. in Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS., 6877261, IEEE Computer Society, pp. 263-272, 28th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2014, Phoenix, AZ, United States, 14/5/19. https://doi.org/10.1109/IPDPS.2014.37
Fujiwara I, Koibuchi M, Matsutani H, Casanova H. Skywalk: A topology for HPC networks with low-delay switches. In Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS. IEEE Computer Society. 2014. p. 263-272. 6877261 https://doi.org/10.1109/IPDPS.2014.37
Fujiwara, Ikki ; Koibuchi, Michihiro ; Matsutani, Hiroki ; Casanova, Henri. / Skywalk : A topology for HPC networks with low-delay switches. Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS. IEEE Computer Society, 2014. pp. 263-272
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