SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricated in 2.1mm 4.2mm × 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage scaling.

Original languageEnglish
Title of host publicationIEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings
DOIs
Publication statusPublished - 2011
Event14th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIV - Yokohama, Japan
Duration: 2011 Apr 202011 Apr 22

Publication series

NameIEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings

Other

Other14th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIV
CountryJapan
CityYokohama
Period11/4/2011/4/22

Keywords

  • 65nmCMOS
  • Low Power
  • Reconfigurable System

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H., & Kondo, M. (2011). SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. In IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings [5890918] (IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings). https://doi.org/10.1109/COOLCHIPS.2011.5890918