Slightly-slacked dropout for improving neural network learning on FPGA

Sota Sawaguchi; Hiroaki Nishi

doi:10.1016/j.icte.2018.04.006

Slightly-slacked dropout for improving neural network learning on FPGA

Sota Sawaguchi, Hiroaki Nishi

Department of System Design Engineering

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

Neural Network Learning (NNL) is compute-intensive. It often involves a dropout technique which effectively regularizes the network to avoid overfitting. As such, a hardware accelerator for dropout NNL has been proposed; however, the existing method encounters a huge transfer cost between hardware and software. This paper proposes Slightly-Slacked Dropout (SS-Dropout), a novel deterministic dropout technique to address the transfer cost while accelerating the process. Experimental results show that our SS-Dropout technique improves both the usual and dropout NNL accelerator, i.e., 1.55 times speed-up and three order-of-magnitude less transfer cost, respectively.

Original language	English
Pages (from-to)	75-80
Number of pages	6
Journal	ICT Express
Volume	4
Issue number	2
DOIs	https://doi.org/10.1016/j.icte.2018.04.006
Publication status	Published - 2018 Jun

Keywords

Dropout technique
Mini-batch SGD algorithm
Neural Network
SoC FPGA

ASJC Scopus subject areas

Software
Information Systems
Hardware and Architecture
Computer Networks and Communications
Artificial Intelligence

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10.1016/j.icte.2018.04.006

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title = "Slightly-slacked dropout for improving neural network learning on FPGA",

abstract = "Neural Network Learning (NNL) is compute-intensive. It often involves a dropout technique which effectively regularizes the network to avoid overfitting. As such, a hardware accelerator for dropout NNL has been proposed; however, the existing method encounters a huge transfer cost between hardware and software. This paper proposes Slightly-Slacked Dropout (SS-Dropout), a novel deterministic dropout technique to address the transfer cost while accelerating the process. Experimental results show that our SS-Dropout technique improves both the usual and dropout NNL accelerator, i.e., 1.55 times speed-up and three order-of-magnitude less transfer cost, respectively.",

keywords = "Dropout technique, Mini-batch SGD algorithm, Neural Network, SoC FPGA",

author = "Sota Sawaguchi and Hiroaki Nishi",

note = "Funding Information: This work was partially supported by MEXT/JSPS KAKENHI Grant (B) Number JP16H04455 and JP17H01739 , through funding received from SECOM Science and Technology Foundation of the R&D project “Design of Information and Communication Platform for Future Smart Community Services” by the Ministry of Internal Affairs and Communications of Japan, and from Keio Univ. Global Smart Society Creation Project Research. ",

year = "2018",

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AU - Nishi, Hiroaki

N1 - Funding Information: This work was partially supported by MEXT/JSPS KAKENHI Grant (B) Number JP16H04455 and JP17H01739 , through funding received from SECOM Science and Technology Foundation of the R&D project “Design of Information and Communication Platform for Future Smart Community Services” by the Ministry of Internal Affairs and Communications of Japan, and from Keio Univ. Global Smart Society Creation Project Research.

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