SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture

Masashi Sasahara, Jun Terada, Luo Zhou, Kalidou Gaye, Jun Ichi Yamato, Satoshi Ogura, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Simple Serial Synchronized (SSS) Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and also solves the pin-limitation problem. Here, design, implementation, and evaluation of a multiprocessor prototype called SNAIL with the SSS-MIN are presented. The heart of SNAIL is the prototype 1 μ CMOS SSS-MIN gate array chip which exchanges packets from 16 inputs with 50MHz clock. The message combining is implemented only with 20% increases of the hardware. From the empirical evaluation with some application programs, it appears that the latency and synchronization overhead of the SSSMIN are tolerable, and the bandwidth of the SSS-MIN is sufficient. Although the performance improvement with the bit serial message combine is not so large (1%) when instructions are stored in the local memory, it becomes up to 400% when instructions are stored in the shared memory.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Parallel Processing
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume1
ISBN (Print)0849324939, 9780849324932
DOIs
Publication statusPublished - 1994
Event23rd International Conference on Parallel Processing, ICPP 1994 - Raleigh, NC, United States
Duration: 1994 Aug 151994 Aug 19

Other

Other23rd International Conference on Parallel Processing, ICPP 1994
CountryUnited States
CityRaleigh, NC
Period94/8/1594/8/19

Fingerprint

Multistage Interconnection Networks
Network Architecture
Multiprocessor
Network architecture
Data storage equipment
Application programs
Computer hardware
Clocks
Prototype
Synchronization
Bandwidth
Evaluation
Shared Memory
Communication
Latency
Simplify
Chip
Hardware
Sufficient
Module

ASJC Scopus subject areas

  • Software
  • Mathematics(all)
  • Hardware and Architecture

Cite this

Sasahara, M., Terada, J., Zhou, L., Gaye, K., Yamato, J. I., Ogura, S., & Amano, H. (1994). SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. In Proceedings of the International Conference on Parallel Processing (Vol. 1). [4115704] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.1994.182

SNAIL : A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. / Sasahara, Masashi; Terada, Jun; Zhou, Luo; Gaye, Kalidou; Yamato, Jun Ichi; Ogura, Satoshi; Amano, Hideharu.

Proceedings of the International Conference on Parallel Processing. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 1994. 4115704.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sasahara, M, Terada, J, Zhou, L, Gaye, K, Yamato, JI, Ogura, S & Amano, H 1994, SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. in Proceedings of the International Conference on Parallel Processing. vol. 1, 4115704, Institute of Electrical and Electronics Engineers Inc., 23rd International Conference on Parallel Processing, ICPP 1994, Raleigh, NC, United States, 94/8/15. https://doi.org/10.1109/ICPP.1994.182
Sasahara M, Terada J, Zhou L, Gaye K, Yamato JI, Ogura S et al. SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. In Proceedings of the International Conference on Parallel Processing. Vol. 1. Institute of Electrical and Electronics Engineers Inc. 1994. 4115704 https://doi.org/10.1109/ICPP.1994.182
Sasahara, Masashi ; Terada, Jun ; Zhou, Luo ; Gaye, Kalidou ; Yamato, Jun Ichi ; Ogura, Satoshi ; Amano, Hideharu. / SNAIL : A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. Proceedings of the International Conference on Parallel Processing. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 1994.
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