Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel

Toshinori Numata, Masumi Saitoh, Yukio Nakabayashi, Kensuke Ota, Ken Uchida

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting 〈100〉 NW channel instead of 〈110〉 NW, I on = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Parasitic capacitance increase due to the spacer thinning is minimal. Heavily-doped poly-Si gate induces vertically compressive strain in NW. Ion increase of 43% is achieved by the additive strain effect of heavily-doped poly-Si gate and tensile stress liner.

    Original languageEnglish
    Title of host publicationICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
    Pages37-40
    Number of pages4
    DOIs
    Publication statusPublished - 2010 Dec 1
    Event2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
    Duration: 2010 Nov 12010 Nov 4

    Publication series

    NameICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

    Other

    Other2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
    CountryChina
    CityShanghai
    Period10/11/110/11/4

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    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Numata, T., Saitoh, M., Nakabayashi, Y., Ota, K., & Uchida, K. (2010). Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 37-40). [5667859] (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2010.5667859