Abstract
An ultralow-voltage performance is investigated in nanowire transistors (NW Tr.) CMOS circuits. SPICE model parameters of BSIM4 are extracted from measurement data of NW Tr. fabricated on 300-mm SOI wafer. The delay time and the power consumption are examined between nanowire and bulk-Si CMOS circuits. The operation voltage of a nanowire CMOS inverter with an ideal subthreshold slope can be reduced by 300 mV from that of the bulk-Si CMOS inverter. NW-Tr.-based circuits under voltage scaling have immunity from supplying voltage fluctuation and suppression of operation delay variation.
| Original language | English |
|---|---|
| Article number | 6471797 |
| Pages (from-to) | 1451-1456 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 60 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2013 |
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Keywords
- CMOS circuit
- low power
- nanowire transistor
- parameter extraction
- SPICE parameter
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
SPICE-based performance analysis of trigate silicon nanowire CMOS circuits. / Tanaka, Chika; Saitoh, Masumi; Ota, Kensuke; Uchida, Ken; Numata, Toshinori.
In: IEEE Transactions on Electron Devices, Vol. 60, No. 4, 6471797, 2013, p. 1451-1456.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - SPICE-based performance analysis of trigate silicon nanowire CMOS circuits
AU - Tanaka, Chika
AU - Saitoh, Masumi
AU - Ota, Kensuke
AU - Uchida, Ken
AU - Numata, Toshinori
PY - 2013
Y1 - 2013
N2 - An ultralow-voltage performance is investigated in nanowire transistors (NW Tr.) CMOS circuits. SPICE model parameters of BSIM4 are extracted from measurement data of NW Tr. fabricated on 300-mm SOI wafer. The delay time and the power consumption are examined between nanowire and bulk-Si CMOS circuits. The operation voltage of a nanowire CMOS inverter with an ideal subthreshold slope can be reduced by 300 mV from that of the bulk-Si CMOS inverter. NW-Tr.-based circuits under voltage scaling have immunity from supplying voltage fluctuation and suppression of operation delay variation.
AB - An ultralow-voltage performance is investigated in nanowire transistors (NW Tr.) CMOS circuits. SPICE model parameters of BSIM4 are extracted from measurement data of NW Tr. fabricated on 300-mm SOI wafer. The delay time and the power consumption are examined between nanowire and bulk-Si CMOS circuits. The operation voltage of a nanowire CMOS inverter with an ideal subthreshold slope can be reduced by 300 mV from that of the bulk-Si CMOS inverter. NW-Tr.-based circuits under voltage scaling have immunity from supplying voltage fluctuation and suppression of operation delay variation.
KW - CMOS circuit
KW - low power
KW - nanowire transistor
KW - parameter extraction
KW - SPICE parameter
UR - http://www.scopus.com/inward/record.url?scp=84875528617&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84875528617&partnerID=8YFLogxK
U2 - 10.1109/TED.2013.2247607
DO - 10.1109/TED.2013.2247607
M3 - Article
VL - 60
SP - 1451
EP - 1456
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 4
M1 - 6471797
ER -