SPICE-based performance analysis of trigate silicon nanowire CMOS circuits

Chika Tanaka, Masumi Saitoh, Kensuke Ota, Ken Uchida, Toshinori Numata

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

An ultralow-voltage performance is investigated in nanowire transistors (NW Tr.) CMOS circuits. SPICE model parameters of BSIM4 are extracted from measurement data of NW Tr. fabricated on 300-mm SOI wafer. The delay time and the power consumption are examined between nanowire and bulk-Si CMOS circuits. The operation voltage of a nanowire CMOS inverter with an ideal subthreshold slope can be reduced by 300 mV from that of the bulk-Si CMOS inverter. NW-Tr.-based circuits under voltage scaling have immunity from supplying voltage fluctuation and suppression of operation delay variation.

Original languageEnglish
Article number6471797
Pages (from-to)1451-1456
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume60
Issue number4
DOIs
Publication statusPublished - 2013 Mar 11

    Fingerprint

Keywords

  • CMOS circuit
  • SPICE parameter
  • low power
  • nanowire transistor
  • parameter extraction

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this