Abstract
An ultralow-voltage performance is investigated in nanowire transistors (NW Tr.) CMOS circuits. SPICE model parameters of BSIM4 are extracted from measurement data of NW Tr. fabricated on 300-mm SOI wafer. The delay time and the power consumption are examined between nanowire and bulk-Si CMOS circuits. The operation voltage of a nanowire CMOS inverter with an ideal subthreshold slope can be reduced by 300 mV from that of the bulk-Si CMOS inverter. NW-Tr.-based circuits under voltage scaling have immunity from supplying voltage fluctuation and suppression of operation delay variation.
| Original language | English |
|---|---|
| Article number | 6471797 |
| Pages (from-to) | 1451-1456 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 60 |
| Issue number | 4 |
| DOIs | |
| Publication status | Published - 2013 Mar 11 |
Keywords
- CMOS circuit
- SPICE parameter
- low power
- nanowire transistor
- parameter extraction
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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Cite this
Tanaka, C., Saitoh, M., Ota, K., Uchida, K., & Numata, T. (2013). SPICE-based performance analysis of trigate silicon nanowire CMOS circuits. IEEE Transactions on Electron Devices, 60(4), 1451-1456. [6471797]. https://doi.org/10.1109/TED.2013.2247607