SPICE-based performance analysis of trigate silicon nanowire CMOS circuits

Chika Tanaka; Masumi Saitoh; Kensuke Ota; Ken Uchida; Toshinori Numata

doi:10.1109/TED.2013.2247607

SPICE-based performance analysis of trigate silicon nanowire CMOS circuits

Chika Tanaka, Masumi Saitoh, Kensuke Ota, Ken Uchida, Toshinori Numata

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

An ultralow-voltage performance is investigated in nanowire transistors (NW Tr.) CMOS circuits. SPICE model parameters of BSIM4 are extracted from measurement data of NW Tr. fabricated on 300-mm SOI wafer. The delay time and the power consumption are examined between nanowire and bulk-Si CMOS circuits. The operation voltage of a nanowire CMOS inverter with an ideal subthreshold slope can be reduced by 300 mV from that of the bulk-Si CMOS inverter. NW-Tr.-based circuits under voltage scaling have immunity from supplying voltage fluctuation and suppression of operation delay variation.

Original language	English
Article number	6471797
Pages (from-to)	1451-1456
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	60
Issue number	4
DOIs	https://doi.org/10.1109/TED.2013.2247607
Publication status	Published - 2013 Mar 11

Keywords

CMOS circuit
SPICE parameter
low power
nanowire transistor
parameter extraction

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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author = "Chika Tanaka and Masumi Saitoh and Kensuke Ota and Ken Uchida and Toshinori Numata",

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AU - Tanaka, Chika

AU - Saitoh, Masumi

AU - Ota, Kensuke

AU - Uchida, Ken

AU - Numata, Toshinori

PY - 2013/3/11

Y1 - 2013/3/11

N2 - An ultralow-voltage performance is investigated in nanowire transistors (NW Tr.) CMOS circuits. SPICE model parameters of BSIM4 are extracted from measurement data of NW Tr. fabricated on 300-mm SOI wafer. The delay time and the power consumption are examined between nanowire and bulk-Si CMOS circuits. The operation voltage of a nanowire CMOS inverter with an ideal subthreshold slope can be reduced by 300 mV from that of the bulk-Si CMOS inverter. NW-Tr.-based circuits under voltage scaling have immunity from supplying voltage fluctuation and suppression of operation delay variation.

AB - An ultralow-voltage performance is investigated in nanowire transistors (NW Tr.) CMOS circuits. SPICE model parameters of BSIM4 are extracted from measurement data of NW Tr. fabricated on 300-mm SOI wafer. The delay time and the power consumption are examined between nanowire and bulk-Si CMOS circuits. The operation voltage of a nanowire CMOS inverter with an ideal subthreshold slope can be reduced by 300 mV from that of the bulk-Si CMOS inverter. NW-Tr.-based circuits under voltage scaling have immunity from supplying voltage fluctuation and suppression of operation delay variation.

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KW - parameter extraction

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SPICE-based performance analysis of trigate silicon nanowire CMOS circuits

Abstract

Keywords

ASJC Scopus subject areas

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