Split capacitor DAC mismatch calibration in successive approximation ADC

Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

Charge redistribution based successive approximation (SA) analog-to-digital converter (ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter (CDAC) technique implements two sets of binary-weighted capacitor arrays connected by a bridge capacitor so as to reduce both input load capacitance and area. However, capacitor mismatches degrade ADC performance in terms of DNL and INL. In this work, a split CDAC mismatch calibration method is proposed. A bridge capacitor larger than conventional design is implemented so that a tunable capacitor can be added in parallel with the lower-weight capacitor array to compensate for mismatches. To guarantee correct CDAC calibration, comparator offset is cancelled using a digital timing control charge compensation technique. To further reduce the input load capacitance, an extra unit capacitor is added to the higher-weight capacitor array. Instead of the lower-weight capacitor array, the extra unit capacitor and the higher-weight capacitor array sample analog input signal. An 8-bit SA ADC with 4-bit + 4-bit split CDAC has been implemented in a 65 nm CMOS process. The ADC has an input capacitance of 180 fF and occupies an active area of 0.03mm2. Measured results of +0.2/-0.3LSB DNL and +0.3/-0.3LSB INL have been achieved after calibration.

Original languageEnglish
Pages (from-to)295-302
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE93-C
Issue number3
DOIs
Publication statusPublished - 2010

Fingerprint

Digital to analog conversion
Capacitors
Calibration
Capacitance

Keywords

  • ADC
  • Calibration
  • Comparator
  • Split capacitor DAC
  • Successive approximation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Split capacitor DAC mismatch calibration in successive approximation ADC. / Chen, Yanfei; Zhu, Xiaolei; Tamura, Hirotaka; Kibune, Masaya; Tomita, Yasumoto; Hamada, Takayuki; Yoshioka, Masato; Ishikawa, Kiyoshi; Takayama, Takeshi; Ogawa, Junji; Tsukamoto, Sanroku; Kuroda, Tadahiro.

In: IEICE Transactions on Electronics, Vol. E93-C, No. 3, 2010, p. 295-302.

Research output: Contribution to journalArticle

Chen, Y, Zhu, X, Tamura, H, Kibune, M, Tomita, Y, Hamada, T, Yoshioka, M, Ishikawa, K, Takayama, T, Ogawa, J, Tsukamoto, S & Kuroda, T 2010, 'Split capacitor DAC mismatch calibration in successive approximation ADC', IEICE Transactions on Electronics, vol. E93-C, no. 3, pp. 295-302. https://doi.org/10.1587/transele.E93.C.295
Chen, Yanfei ; Zhu, Xiaolei ; Tamura, Hirotaka ; Kibune, Masaya ; Tomita, Yasumoto ; Hamada, Takayuki ; Yoshioka, Masato ; Ishikawa, Kiyoshi ; Takayama, Takeshi ; Ogawa, Junji ; Tsukamoto, Sanroku ; Kuroda, Tadahiro. / Split capacitor DAC mismatch calibration in successive approximation ADC. In: IEICE Transactions on Electronics. 2010 ; Vol. E93-C, No. 3. pp. 295-302.
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