Split capacitor DAC mismatch calibration in successive approximation ADC

Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    100 Citations (Scopus)

    Abstract

    A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.

    Original languageEnglish
    Title of host publication2009 IEEE Custom Integrated Circuits Conference, CICC '09
    Pages279-282
    Number of pages4
    DOIs
    Publication statusPublished - 2009 Dec 1
    Event2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States
    Duration: 2009 Sep 132009 Sep 16

    Publication series

    NameProceedings of the Custom Integrated Circuits Conference
    ISSN (Print)0886-5930

    Other

    Other2009 IEEE Custom Integrated Circuits Conference, CICC '09
    CountryUnited States
    CitySan Jose, CA
    Period09/9/1309/9/16

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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  • Cite this

    Chen, Y., Zhu, X., Tamura, H., Kibune, M., Tomita, Y., Hamada, T., Yoshioka, M., Ishikawa, K., Takayama, T., Ogawa, J., Tsukamoto, S., & Kuroda, T. (2009). Split capacitor DAC mismatch calibration in successive approximation ADC. In 2009 IEEE Custom Integrated Circuits Conference, CICC '09 (pp. 279-282). [5280859] (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2009.5280859