Split capacitor DAC mismatch calibration in successive approximation ADC

Yanfei Chen; Xiaolei Zhu; Hirotaka Tamura; Masaya Kibune; Yasumoto Tomita; Takayuki Hamada; Masato Yoshioka; Kiyoshi Ishikawa; Takeshi Takayama; Junji Ogawa; Sanroku Tsukamoto; Tadahiro Kuroda

doi:10.1109/CICC.2009.5280859

Split capacitor DAC mismatch calibration in successive approximation ADC

Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

121 Citations (Scopus)

Abstract

A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.

Original language	English
Title of host publication	2009 IEEE Custom Integrated Circuits Conference, CICC '09
Pages	279-282
Number of pages	4
DOIs	https://doi.org/10.1109/CICC.2009.5280859
Publication status	Published - 2009
Event	2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States Duration: 2009 Sept 13 → 2009 Sept 16

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	2009 IEEE Custom Integrated Circuits Conference, CICC '09
Country/Territory	United States
City	San Jose, CA
Period	09/9/13 → 09/9/16

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/CICC.2009.5280859

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Chen, Y., Zhu, X., Tamura, H., Kibune, M., Tomita, Y., Hamada, T., Yoshioka, M., Ishikawa, K., Takayama, T., Ogawa, J., Tsukamoto, S., & Kuroda, T. (2009). Split capacitor DAC mismatch calibration in successive approximation ADC. In 2009 IEEE Custom Integrated Circuits Conference, CICC '09 (pp. 279-282). [5280859] (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2009.5280859

Chen, Y, Zhu, X, Tamura, H, Kibune, M, Tomita, Y, Hamada, T, Yoshioka, M, Ishikawa, K, Takayama, T, Ogawa, J, Tsukamoto, S & Kuroda, T 2009, Split capacitor DAC mismatch calibration in successive approximation ADC. in 2009 IEEE Custom Integrated Circuits Conference, CICC '09., 5280859, Proceedings of the Custom Integrated Circuits Conference, pp. 279-282, 2009 IEEE Custom Integrated Circuits Conference, CICC '09, San Jose, CA, United States, 09/9/13. https://doi.org/10.1109/CICC.2009.5280859

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title = "Split capacitor DAC mismatch calibration in successive approximation ADC",

abstract = "A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.",

author = "Yanfei Chen and Xiaolei Zhu and Hirotaka Tamura and Masaya Kibune and Yasumoto Tomita and Takayuki Hamada and Masato Yoshioka and Kiyoshi Ishikawa and Takeshi Takayama and Junji Ogawa and Sanroku Tsukamoto and Tadahiro Kuroda",

year = "2009",

doi = "10.1109/CICC.2009.5280859",

language = "English",

isbn = "9781424440726",

series = "Proceedings of the Custom Integrated Circuits Conference",

pages = "279--282",

booktitle = "2009 IEEE Custom Integrated Circuits Conference, CICC '09",

note = "2009 IEEE Custom Integrated Circuits Conference, CICC '09 ; Conference date: 13-09-2009 Through 16-09-2009",

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T1 - Split capacitor DAC mismatch calibration in successive approximation ADC

AU - Chen, Yanfei

AU - Zhu, Xiaolei

AU - Tamura, Hirotaka

AU - Kibune, Masaya

AU - Tomita, Yasumoto

AU - Hamada, Takayuki

AU - Yoshioka, Masato

AU - Ishikawa, Kiyoshi

AU - Takayama, Takeshi

AU - Ogawa, Junji

AU - Tsukamoto, Sanroku

AU - Kuroda, Tadahiro

PY - 2009

Y1 - 2009

N2 - A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.

AB - A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.

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U2 - 10.1109/CICC.2009.5280859

DO - 10.1109/CICC.2009.5280859

M3 - Conference contribution

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SN - 9781424440726

T3 - Proceedings of the Custom Integrated Circuits Conference

SP - 279

EP - 282

BT - 2009 IEEE Custom Integrated Circuits Conference, CICC '09

T2 - 2009 IEEE Custom Integrated Circuits Conference, CICC '09

Y2 - 13 September 2009 through 16 September 2009

ER -

Split capacitor DAC mismatch calibration in successive approximation ADC

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