Stream applications on the dynamically reconfigurable processor

Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

29 Citations (Scopus)

Abstract

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C6713 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

Original languageEnglish
Title of host publicationProceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04
EditorsO. Diessel, J. Williams
Pages137-144
Number of pages8
Publication statusPublished - 2004
Event2004 IEEE International Conference on Field-Programmable Technology, FPT '04 - Brisbane, Australia
Duration: 2004 Dec 62004 Dec 8

Other

Other2004 IEEE International Conference on Field-Programmable Technology, FPT '04
CountryAustralia
CityBrisbane
Period04/12/604/12/8

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Program processors
Electronic equipment
Networks (circuits)

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Suzuki, M., Hasegawa, Y., Yamada, Y., Kaneko, N., Deguchi, K., Amano, H., ... Awashima, T. (2004). Stream applications on the dynamically reconfigurable processor. In O. Diessel, & J. Williams (Eds.), Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04 (pp. 137-144)

Stream applications on the dynamically reconfigurable processor. / Suzuki, Masayasu; Hasegawa, Yohei; Yamada, Yutaka; Kaneko, Naoto; Deguchi, Katsuaki; Amano, Hideharu; Anjo, Kenichiro; Motomura, Masato; Wakabayashi, Kazutoshi; Toi, Takao; Awashima, Toru.

Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. ed. / O. Diessel; J. Williams. 2004. p. 137-144.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Suzuki, M, Hasegawa, Y, Yamada, Y, Kaneko, N, Deguchi, K, Amano, H, Anjo, K, Motomura, M, Wakabayashi, K, Toi, T & Awashima, T 2004, Stream applications on the dynamically reconfigurable processor. in O Diessel & J Williams (eds), Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. pp. 137-144, 2004 IEEE International Conference on Field-Programmable Technology, FPT '04, Brisbane, Australia, 04/12/6.
Suzuki M, Hasegawa Y, Yamada Y, Kaneko N, Deguchi K, Amano H et al. Stream applications on the dynamically reconfigurable processor. In Diessel O, Williams J, editors, Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. 2004. p. 137-144
Suzuki, Masayasu ; Hasegawa, Yohei ; Yamada, Yutaka ; Kaneko, Naoto ; Deguchi, Katsuaki ; Amano, Hideharu ; Anjo, Kenichiro ; Motomura, Masato ; Wakabayashi, Kazutoshi ; Toi, Takao ; Awashima, Toru. / Stream applications on the dynamically reconfigurable processor. Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. editor / O. Diessel ; J. Williams. 2004. pp. 137-144
@inproceedings{9ee997aac0de4fa5b12b3c60dfa9bd30,
title = "Stream applications on the dynamically reconfigurable processor",
abstract = "Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C6713 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.",
author = "Masayasu Suzuki and Yohei Hasegawa and Yutaka Yamada and Naoto Kaneko and Katsuaki Deguchi and Hideharu Amano and Kenichiro Anjo and Masato Motomura and Kazutoshi Wakabayashi and Takao Toi and Toru Awashima",
year = "2004",
language = "English",
isbn = "0780386515",
pages = "137--144",
editor = "O. Diessel and J. Williams",
booktitle = "Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04",

}

TY - GEN

T1 - Stream applications on the dynamically reconfigurable processor

AU - Suzuki, Masayasu

AU - Hasegawa, Yohei

AU - Yamada, Yutaka

AU - Kaneko, Naoto

AU - Deguchi, Katsuaki

AU - Amano, Hideharu

AU - Anjo, Kenichiro

AU - Motomura, Masato

AU - Wakabayashi, Kazutoshi

AU - Toi, Takao

AU - Awashima, Toru

PY - 2004

Y1 - 2004

N2 - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C6713 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

AB - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C6713 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

UR - http://www.scopus.com/inward/record.url?scp=20844447143&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=20844447143&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:20844447143

SN - 0780386515

SP - 137

EP - 144

BT - Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

A2 - Diessel, O.

A2 - Williams, J.

ER -