Stress Concentration and Profile under Thermal Cycling Test in Power Device Heat Dissipation Structures Using Double-Side Chip Bonding with Ag Sintered Layer on Cu Plate

Kensuke Osonoe, Masaaki Aoki, Takahiro Asai, Yoshio Murakami, Hitoshi Kida, Goro Yoshinari, Nobuhiko Nakano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Power semiconductor devices and modules need highly efficient heat dissipation system having a chip bonding layer with high thermal conductance and reliability. Ag sintering chip-Attachment has several advantages for heat dissipation. This work clarifies the thermal stress profiles under thermal cycling test by 3D multi-physics solver for double-side and single-side direct bonding structures with Ag sintered layers on Cu plates. Results show that the maximum stress point is at Si chip corner in the double-side bonding structure with Ag sintered layers, and the maximum stress point is at bonding layer corner in the single-side bonding structure. The stress values of Ag sintered layer in double-side bonding are much lower than the stress values of single-side bonding. In contrast the maximum stress value of Si chip in double-side bonding is higher than that in single-side bonding, because the upward convex warp of Si is suppressed in double-side bonding. It was found that the maximum stress value at Si chip corner for Ag sintered bonding is lower than that for conventional solder in double-side bonding structure. There is also the bonding layer TCE value for minimizing the thermal stress at bonding center, since the stress at bonding interface is thought to be caused by the difference of thermal expansion between Ag sintered layer and Cu plate.

Original languageEnglish
Title of host publicationProceedings - ECTC 2016: 66th Electronic Components and Technology Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1047-1053
Number of pages7
Volume2016-August
ISBN (Electronic)9781509012039
DOIs
Publication statusPublished - 2016 Aug 16
Event66th IEEE Electronic Components and Technology Conference, ECTC 2016 - Las Vegas, United States
Duration: 2016 May 312016 Jun 3

Other

Other66th IEEE Electronic Components and Technology Conference, ECTC 2016
CountryUnited States
CityLas Vegas
Period16/5/3116/6/3

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Keywords

  • Ag sintering
  • Chip attachment
  • Double-side cooling
  • Multi-physics solver
  • Power semiconductor devices
  • Stress and strain analysis
  • Thermal cycling test

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Osonoe, K., Aoki, M., Asai, T., Murakami, Y., Kida, H., Yoshinari, G., & Nakano, N. (2016). Stress Concentration and Profile under Thermal Cycling Test in Power Device Heat Dissipation Structures Using Double-Side Chip Bonding with Ag Sintered Layer on Cu Plate. In Proceedings - ECTC 2016: 66th Electronic Components and Technology Conference (Vol. 2016-August, pp. 1047-1053). [7545554] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECTC.2016.79