Stress engineering for high-performance MOSFETs

Ken Uchida

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Since the conventional strategy, namely scaling of device dimensions in ultimately scaled shorter-channel-length MOS transistors, is less effective to enhance transistor performance, another strategy is strongly demanded. Stress engineering is one of the most promising performance boosters for the ultimately scaled MOS transistors. In this paper, we will introduce the physical mechanisms of the drain current enhancement induced by stress. We will discuss the mechanisms based on the band structure modification by stress. The effectiveness of the stress engineering in future devices is also prospected.

Original languageEnglish
Pages (from-to)301-305
Number of pages5
JournalJournal of the Vacuum Society of Japan
Volume51
Issue number5
Publication statusPublished - 2008
Externally publishedYes

Fingerprint

field effect transistors
engineering
transistors
MOSFET devices
boosters
Drain current
Band structure
Transistors
scaling
augmentation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Surfaces and Interfaces

Cite this

Stress engineering for high-performance MOSFETs. / Uchida, Ken.

In: Journal of the Vacuum Society of Japan, Vol. 51, No. 5, 2008, p. 301-305.

Research output: Contribution to journalArticle

Uchida, Ken. / Stress engineering for high-performance MOSFETs. In: Journal of the Vacuum Society of Japan. 2008 ; Vol. 51, No. 5. pp. 301-305.
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