Substrate noise influence on circuit performance in variable threshold-voltage scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper investigates substrate noise influence on circuit performance in a variable threshold-voltage scheme (VT scheme) where threshold voltage is dynamically varied by substrate-bias control to reduce active power dissipation. It is experimentally examined that substrate-bias can be controlled stably with very few substrate-contacts. Measured tracking jitter of a delay-locked loop implemented by interconnections in an 8mm-square gate array does not degrade even when substrate-contacts are removed except for one at every strip of p-sub and n-well. A 2mm-square discrete cosine transform core processor with no substrate-contact except in its periphery operates at supply voltages from 1.3V to above 3V even though it employs small-swing differential dynamic pass-transistor logic. No performance degradation nor latchup is observed in these chips even when 100kΩ resistance is added to the substrate. These experimental results demonstrate noise immunity of the VT scheme, and indicate the possibility that the VT scheme can be applied to existing macro design easily.

Original languageEnglish
Title of host publicationInternational Symposium on Low Power Electronics and Design, Digest of Technical Papers
PublisherIEEE
Pages309-312
Number of pages4
Publication statusPublished - 1996
Externally publishedYes
EventProceedings of the 1996 International Symposium on Low Power Electronics and Design - Monterey, CA, USA
Duration: 1996 Aug 121996 Aug 14

Other

OtherProceedings of the 1996 International Symposium on Low Power Electronics and Design
CityMonterey, CA, USA
Period96/8/1296/8/14

Fingerprint

Threshold voltage
Networks (circuits)
Substrates
Electric potential
Discrete cosine transforms
Jitter
Macros
Energy dissipation
Transistors
Degradation

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Kuroda, T., Fujita, T., Mita, S., Mori, T., Matsuo, K., Kakumu, M., & Sakurai, T. (1996). Substrate noise influence on circuit performance in variable threshold-voltage scheme. In International Symposium on Low Power Electronics and Design, Digest of Technical Papers (pp. 309-312). IEEE.

Substrate noise influence on circuit performance in variable threshold-voltage scheme. / Kuroda, Tadahiro; Fujita, Tetsuya; Mita, Shinji; Mori, Toshiaki; Matsuo, Kenji; Kakumu, Masakazu; Sakurai, Takayasu.

International Symposium on Low Power Electronics and Design, Digest of Technical Papers. IEEE, 1996. p. 309-312.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kuroda, T, Fujita, T, Mita, S, Mori, T, Matsuo, K, Kakumu, M & Sakurai, T 1996, Substrate noise influence on circuit performance in variable threshold-voltage scheme. in International Symposium on Low Power Electronics and Design, Digest of Technical Papers. IEEE, pp. 309-312, Proceedings of the 1996 International Symposium on Low Power Electronics and Design, Monterey, CA, USA, 96/8/12.
Kuroda T, Fujita T, Mita S, Mori T, Matsuo K, Kakumu M et al. Substrate noise influence on circuit performance in variable threshold-voltage scheme. In International Symposium on Low Power Electronics and Design, Digest of Technical Papers. IEEE. 1996. p. 309-312
Kuroda, Tadahiro ; Fujita, Tetsuya ; Mita, Shinji ; Mori, Toshiaki ; Matsuo, Kenji ; Kakumu, Masakazu ; Sakurai, Takayasu. / Substrate noise influence on circuit performance in variable threshold-voltage scheme. International Symposium on Low Power Electronics and Design, Digest of Technical Papers. IEEE, 1996. pp. 309-312
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