Abstract
Superpixel segmentation is a very popular image segmentation technique used in various computer vision tasks. Recently, a number of superpixel algorithms have been proposed in literature. One such algorithm is considered as the-state-of-the-art in superpixel segmentation: Simple Linear Iterative Clustering or SLIC. However, its original implementation has a long execution time on high performance processors designed within the common mobile and enterprise applications, as well on high-end processors such as Intel Xeon. Overall, the execution time for single-threaded implementation is considered critical for real-time or near real-time applications. In this paper, we explore the possibility of accelerating parts of the SLIC image segmentation critical for performance, by designing the image segmentation accelerator for Intel's Arria 10 SoC. We propose a novel architecture to enable hardware acceleration by addressing the problem of hardware/software partitioning to minimize the overall program latency.
Original language | English |
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Title of host publication | Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 55-60 |
Number of pages | 6 |
ISBN (Electronic) | 9781538657546 |
DOIs | |
Publication status | Published - 2018 Jul 11 |
Event | 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018 - Budapest, Hungary Duration: 2018 Apr 25 → 2018 Apr 27 |
Other
Other | 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018 |
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Country | Hungary |
City | Budapest |
Period | 18/4/25 → 18/4/27 |
Keywords
- Computer Vision
- Hardware Acceleration
- Image segmentation
- OpenCL
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality