Synthesis for SoC architecture using VCores

Hiroaki Nishi, M. Muraoka, R. K. Morizawa, H. Yokota, H. Hamada

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

In this paper, we propose a novel architecture synthesis method for SoCs using VCores (virtual cores). VCores are reusable and configurable high-level descriptions. An initial SoC architecture, which consists of a CPU, buses, and peripherals, is generated, based on an architecture template. The hardware and software tradeoff is possible on the architecture model after assignment of software VCores or hardware VCores. The assignment is based on the results of the architecture's performance estimation. We present a prototype of the synthesis for SoC architecture using VCores and an architecture level design experiment using this prototype.

Original languageEnglish
Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages446-452
Number of pages7
Volume2003-January
ISBN (Print)0780376595
DOIs
Publication statusPublished - 2003
Externally publishedYes
EventAsia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
Duration: 2003 Jan 212003 Jan 24

Other

OtherAsia and South Pacific Design Automation Conference, ASP-DAC 2003
CountryJapan
CityKitakyushu
Period03/1/2103/1/24

Fingerprint

Hardware
Computer peripheral equipment
Program processors
Experiments
System-on-chip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Nishi, H., Muraoka, M., Morizawa, R. K., Yokota, H., & Hamada, H. (2003). Synthesis for SoC architecture using VCores. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (Vol. 2003-January, pp. 446-452). [1195057] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2003.1195057

Synthesis for SoC architecture using VCores. / Nishi, Hiroaki; Muraoka, M.; Morizawa, R. K.; Yokota, H.; Hamada, H.

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2003-January Institute of Electrical and Electronics Engineers Inc., 2003. p. 446-452 1195057.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nishi, H, Muraoka, M, Morizawa, RK, Yokota, H & Hamada, H 2003, Synthesis for SoC architecture using VCores. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. vol. 2003-January, 1195057, Institute of Electrical and Electronics Engineers Inc., pp. 446-452, Asia and South Pacific Design Automation Conference, ASP-DAC 2003, Kitakyushu, Japan, 03/1/21. https://doi.org/10.1109/ASPDAC.2003.1195057
Nishi H, Muraoka M, Morizawa RK, Yokota H, Hamada H. Synthesis for SoC architecture using VCores. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2003-January. Institute of Electrical and Electronics Engineers Inc. 2003. p. 446-452. 1195057 https://doi.org/10.1109/ASPDAC.2003.1195057
Nishi, Hiroaki ; Muraoka, M. ; Morizawa, R. K. ; Yokota, H. ; Hamada, H. / Synthesis for SoC architecture using VCores. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2003-January Institute of Electrical and Electronics Engineers Inc., 2003. pp. 446-452
@inproceedings{9965c319b17c48b79048a61e5734f411,
title = "Synthesis for SoC architecture using VCores",
abstract = "In this paper, we propose a novel architecture synthesis method for SoCs using VCores (virtual cores). VCores are reusable and configurable high-level descriptions. An initial SoC architecture, which consists of a CPU, buses, and peripherals, is generated, based on an architecture template. The hardware and software tradeoff is possible on the architecture model after assignment of software VCores or hardware VCores. The assignment is based on the results of the architecture's performance estimation. We present a prototype of the synthesis for SoC architecture using VCores and an architecture level design experiment using this prototype.",
author = "Hiroaki Nishi and M. Muraoka and Morizawa, {R. K.} and H. Yokota and H. Hamada",
year = "2003",
doi = "10.1109/ASPDAC.2003.1195057",
language = "English",
isbn = "0780376595",
volume = "2003-January",
pages = "446--452",
booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Synthesis for SoC architecture using VCores

AU - Nishi, Hiroaki

AU - Muraoka, M.

AU - Morizawa, R. K.

AU - Yokota, H.

AU - Hamada, H.

PY - 2003

Y1 - 2003

N2 - In this paper, we propose a novel architecture synthesis method for SoCs using VCores (virtual cores). VCores are reusable and configurable high-level descriptions. An initial SoC architecture, which consists of a CPU, buses, and peripherals, is generated, based on an architecture template. The hardware and software tradeoff is possible on the architecture model after assignment of software VCores or hardware VCores. The assignment is based on the results of the architecture's performance estimation. We present a prototype of the synthesis for SoC architecture using VCores and an architecture level design experiment using this prototype.

AB - In this paper, we propose a novel architecture synthesis method for SoCs using VCores (virtual cores). VCores are reusable and configurable high-level descriptions. An initial SoC architecture, which consists of a CPU, buses, and peripherals, is generated, based on an architecture template. The hardware and software tradeoff is possible on the architecture model after assignment of software VCores or hardware VCores. The assignment is based on the results of the architecture's performance estimation. We present a prototype of the synthesis for SoC architecture using VCores and an architecture level design experiment using this prototype.

UR - http://www.scopus.com/inward/record.url?scp=2442475366&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=2442475366&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2003.1195057

DO - 10.1109/ASPDAC.2003.1195057

M3 - Conference contribution

AN - SCOPUS:2442475366

SN - 0780376595

VL - 2003-January

SP - 446

EP - 452

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

PB - Institute of Electrical and Electronics Engineers Inc.

ER -