SystemVerilog assertion for microarchitecture education considering situated nature of learning

A senior project

Ryuichi Takahashi, Yoshiyasu Takefuji

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

SystemVerilog assertion (SVA) is a way to express properties that are expected to be true in a design described in Verilog HDL IEEE1364 standard. We have already reported that legitimate peripheral participation (LPP) works very well for the fine grain microprocessor design education on FPGA where the heart of the system is chosen as the way-in which is the first step for the observation in LPP. We have demonstrated its effectiveness on superscalar design education, while the prior pipeline design education failed. The failure was caused by the top down design methodology guided in the education for the pipelining which appeared to be too difficult. Appropriate scheme to observe the heart of the pipelining is needed. We have found that SVA plays a key role where two senior students succeeded to design pipelined RISC having 3 stages and pipelined CISC having 4 stages in 2 months. White box test by using SVA enables the two senior students to observe the heart of the pipelining very effectively.

Original languageEnglish
Title of host publication2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011
Pages112-113
Number of pages2
DOIs
Publication statusPublished - 2011
Event2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011 - San Diego, CA, United States
Duration: 2011 Jun 52011 Jun 6

Other

Other2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011
CountryUnited States
CitySan Diego, CA
Period11/6/511/6/6

Fingerprint

Education
learning
education
microprocessor
participation
Students
agricultural product
Computer hardware description languages
Reduced instruction set computing
student
Field programmable gate arrays (FPGA)
Microprocessor chips
methodology
Pipelines

Keywords

  • Assertion
  • Legitimate peripheral participation
  • Microarchitecture education
  • Ppipelining
  • SystemVerilog

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Education

Cite this

Takahashi, R., & Takefuji, Y. (2011). SystemVerilog assertion for microarchitecture education considering situated nature of learning: A senior project. In 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011 (pp. 112-113). [5937107] https://doi.org/10.1109/MSE.2011.5937107

SystemVerilog assertion for microarchitecture education considering situated nature of learning : A senior project. / Takahashi, Ryuichi; Takefuji, Yoshiyasu.

2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011. 2011. p. 112-113 5937107.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Takahashi, R & Takefuji, Y 2011, SystemVerilog assertion for microarchitecture education considering situated nature of learning: A senior project. in 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011., 5937107, pp. 112-113, 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011, San Diego, CA, United States, 11/6/5. https://doi.org/10.1109/MSE.2011.5937107
Takahashi R, Takefuji Y. SystemVerilog assertion for microarchitecture education considering situated nature of learning: A senior project. In 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011. 2011. p. 112-113. 5937107 https://doi.org/10.1109/MSE.2011.5937107
Takahashi, Ryuichi ; Takefuji, Yoshiyasu. / SystemVerilog assertion for microarchitecture education considering situated nature of learning : A senior project. 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011. 2011. pp. 112-113
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