Task level pipelining on multiple accelerators via FPGA switch

Takaaki Miyajima; Takuya Kuhara; Toshihiro Hanawa; Hideharu Amano; Taisuke Boku

doi:10.2316/P.2014.811-026

Task level pipelining on multiple accelerators via FPGA switch

Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku

Department of Information and Computer Science

Research output: Contribution to conference › Paper › peer-review

Abstract

We show a task level pipelining on multiple accelerators with PEACH2. PEACH2, which is implemented on FPGA, enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level parallelism. Furthermore, we can process multiple task on multiple accelerators in a pipelined manner. In our evaluation, pipelined application which is implemented in a task level pipelined manner achieves 52% speed up compared to a single GPU.

Original language	English
Pages	267-274
Number of pages	8
DOIs	https://doi.org/10.2316/P.2014.811-026
Publication status	Published - 2014
Event	12th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2014 - Innsbruck, Austria Duration: 2014 Feb 17 → 2014 Feb 19

Other

Other	12th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2014
Country/Territory	Austria
City	Innsbruck
Period	14/2/17 → 14/2/19

Keywords

Accelerator computing
FPGA Interconnect
GPU cluster
Interconnect for accelerators
Task Level Pipeline

ASJC Scopus subject areas

Software

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10.2316/P.2014.811-026

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title = "Task level pipelining on multiple accelerators via FPGA switch",

abstract = "We show a task level pipelining on multiple accelerators with PEACH2. PEACH2, which is implemented on FPGA, enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level parallelism. Furthermore, we can process multiple task on multiple accelerators in a pipelined manner. In our evaluation, pipelined application which is implemented in a task level pipelined manner achieves 52% speed up compared to a single GPU.",

keywords = "Accelerator computing, FPGA Interconnect, GPU cluster, Interconnect for accelerators, Task Level Pipeline",

author = "Takaaki Miyajima and Takuya Kuhara and Toshihiro Hanawa and Hideharu Amano and Taisuke Boku",

year = "2014",

doi = "10.2316/P.2014.811-026",

language = "English",

pages = "267--274",

note = "12th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2014 ; Conference date: 17-02-2014 Through 19-02-2014",

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T1 - Task level pipelining on multiple accelerators via FPGA switch

AU - Miyajima, Takaaki

AU - Kuhara, Takuya

AU - Hanawa, Toshihiro

AU - Amano, Hideharu

AU - Boku, Taisuke

PY - 2014

Y1 - 2014

N2 - We show a task level pipelining on multiple accelerators with PEACH2. PEACH2, which is implemented on FPGA, enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level parallelism. Furthermore, we can process multiple task on multiple accelerators in a pipelined manner. In our evaluation, pipelined application which is implemented in a task level pipelined manner achieves 52% speed up compared to a single GPU.

AB - We show a task level pipelining on multiple accelerators with PEACH2. PEACH2, which is implemented on FPGA, enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level parallelism. Furthermore, we can process multiple task on multiple accelerators in a pipelined manner. In our evaluation, pipelined application which is implemented in a task level pipelined manner achieves 52% speed up compared to a single GPU.

KW - Accelerator computing

KW - FPGA Interconnect

KW - GPU cluster

KW - Interconnect for accelerators

KW - Task Level Pipeline

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M3 - Paper

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T2 - 12th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2014

Y2 - 17 February 2014 through 19 February 2014

ER -

Task level pipelining on multiple accelerators via FPGA switch

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Keywords

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