Abstract
We demonstrate task level pipelining on multiple accelerators with PEACH2. PEACH2 is implmented on FPGA, and enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level pipelined operation. Furthermore, we can processe multiple task on multiple accelerators in a pipelined manner. In our demonstration, application achieves 44% speed up compared to a single GPU.
| Original language | English |
|---|---|
| Title of host publication | FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology |
| Pages | 466-469 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2013 |
| Event | 2013 12th International Conference on Field-Programmable Technology, FPT 2013 - Kyoto, Japan Duration: 2013 Dec 9 → 2013 Dec 11 |
Other
| Other | 2013 12th International Conference on Field-Programmable Technology, FPT 2013 |
|---|---|
| Country | Japan |
| City | Kyoto |
| Period | 13/12/9 → 13/12/11 |
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ASJC Scopus subject areas
- Software
Cite this
Task level pipelining with PEACH2 : An FPGA switching fabric for high performance computing. / Miyajima, Takaaki; Kuhara, Takuya; Hanawa, Toshihiro; Amano, Hideharu; Boku, Taisuke.
FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. 2013. p. 466-469 6718416.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Task level pipelining with PEACH2
T2 - An FPGA switching fabric for high performance computing
AU - Miyajima, Takaaki
AU - Kuhara, Takuya
AU - Hanawa, Toshihiro
AU - Amano, Hideharu
AU - Boku, Taisuke
PY - 2013
Y1 - 2013
N2 - We demonstrate task level pipelining on multiple accelerators with PEACH2. PEACH2 is implmented on FPGA, and enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level pipelined operation. Furthermore, we can processe multiple task on multiple accelerators in a pipelined manner. In our demonstration, application achieves 44% speed up compared to a single GPU.
AB - We demonstrate task level pipelining on multiple accelerators with PEACH2. PEACH2 is implmented on FPGA, and enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level pipelined operation. Furthermore, we can processe multiple task on multiple accelerators in a pipelined manner. In our demonstration, application achieves 44% speed up compared to a single GPU.
UR - http://www.scopus.com/inward/record.url?scp=84894223759&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84894223759&partnerID=8YFLogxK
U2 - 10.1109/FPT.2013.6718416
DO - 10.1109/FPT.2013.6718416
M3 - Conference contribution
SN - 9781479921990
SP - 466
EP - 469
BT - FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology
ER -