Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing

Takaaki Miyajima; Takuya Kuhara; Toshihiro Hanawa; Hideharu Amano; Taisuke Boku

doi:10.1109/FPT.2013.6718416

Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing

Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

We demonstrate task level pipelining on multiple accelerators with PEACH2. PEACH2 is implmented on FPGA, and enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level pipelined operation. Furthermore, we can processe multiple task on multiple accelerators in a pipelined manner. In our demonstration, application achieves 44% speed up compared to a single GPU.

Original language	English
Title of host publication	FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology
Pages	466-469
Number of pages	4
DOIs	https://doi.org/10.1109/FPT.2013.6718416
Publication status	Published - 2013 Dec 1
Event	2013 12th International Conference on Field-Programmable Technology, FPT 2013 - Kyoto, Japan Duration: 2013 Dec 9 → 2013 Dec 11

Publication series

Name	FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology

Other

Other	2013 12th International Conference on Field-Programmable Technology, FPT 2013
Country/Territory	Japan
City	Kyoto
Period	13/12/9 → 13/12/11

ASJC Scopus subject areas

Software

Access to Document

10.1109/FPT.2013.6718416

Cite this

Miyajima, T., Kuhara, T., Hanawa, T., Amano, H., & Boku, T. (2013). Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing. In FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology (pp. 466-469). [6718416] (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology). https://doi.org/10.1109/FPT.2013.6718416

Task level pipelining with PEACH2 : An FPGA switching fabric for high performance computing. / Miyajima, Takaaki; Kuhara, Takuya; Hanawa, Toshihiro et al.

FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. 2013. p. 466-469 6718416 (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Miyajima, T, Kuhara, T, Hanawa, T, Amano, H & Boku, T 2013, Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing. in FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology., 6718416, FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology, pp. 466-469, 2013 12th International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, 13/12/9. https://doi.org/10.1109/FPT.2013.6718416

Miyajima T, Kuhara T, Hanawa T, Amano H, Boku T. Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing. In FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology. 2013. p. 466-469. 6718416. (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology). doi: 10.1109/FPT.2013.6718416

@inproceedings{5fb38450268e4a2895e9ef95090279bf,

title = "Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing",

abstract = "We demonstrate task level pipelining on multiple accelerators with PEACH2. PEACH2 is implmented on FPGA, and enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level pipelined operation. Furthermore, we can processe multiple task on multiple accelerators in a pipelined manner. In our demonstration, application achieves 44% speed up compared to a single GPU.",

author = "Takaaki Miyajima and Takuya Kuhara and Toshihiro Hanawa and Hideharu Amano and Taisuke Boku",

year = "2013",

month = dec,

day = "1",

doi = "10.1109/FPT.2013.6718416",

language = "English",

isbn = "9781479921990",

series = "FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology",

pages = "466--469",

booktitle = "FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology",

note = "2013 12th International Conference on Field-Programmable Technology, FPT 2013 ; Conference date: 09-12-2013 Through 11-12-2013",

}

TY - GEN

T1 - Task level pipelining with PEACH2

T2 - 2013 12th International Conference on Field-Programmable Technology, FPT 2013

AU - Miyajima, Takaaki

AU - Kuhara, Takuya

AU - Hanawa, Toshihiro

AU - Amano, Hideharu

AU - Boku, Taisuke

PY - 2013/12/1

Y1 - 2013/12/1

N2 - We demonstrate task level pipelining on multiple accelerators with PEACH2. PEACH2 is implmented on FPGA, and enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level pipelined operation. Furthermore, we can processe multiple task on multiple accelerators in a pipelined manner. In our demonstration, application achieves 44% speed up compared to a single GPU.

AB - We demonstrate task level pipelining on multiple accelerators with PEACH2. PEACH2 is implmented on FPGA, and enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level pipelined operation. Furthermore, we can processe multiple task on multiple accelerators in a pipelined manner. In our demonstration, application achieves 44% speed up compared to a single GPU.

UR - http://www.scopus.com/inward/record.url?scp=84894223759&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84894223759&partnerID=8YFLogxK

U2 - 10.1109/FPT.2013.6718416

DO - 10.1109/FPT.2013.6718416

M3 - Conference contribution

AN - SCOPUS:84894223759

SN - 9781479921990

T3 - FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology

SP - 466

EP - 469

BT - FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology

Y2 - 9 December 2013 through 11 December 2013

ER -

Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing

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