Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing

Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We demonstrate task level pipelining on multiple accelerators with PEACH2. PEACH2 is implmented on FPGA, and enables ultra low latency direct communication among multiple accelerators over computational nodes. By installing PEACH2, typical high performance computation nodes are tightly coupled. In this environment, application can be accelerated by exploiting not only data level parallelism, but also task level pipelined operation. Furthermore, we can processe multiple task on multiple accelerators in a pipelined manner. In our demonstration, application achieves 44% speed up compared to a single GPU.

Original languageEnglish
Title of host publicationFPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology
Pages466-469
Number of pages4
DOIs
Publication statusPublished - 2013 Dec 1
Event2013 12th International Conference on Field-Programmable Technology, FPT 2013 - Kyoto, Japan
Duration: 2013 Dec 92013 Dec 11

Publication series

NameFPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology

Other

Other2013 12th International Conference on Field-Programmable Technology, FPT 2013
CountryJapan
CityKyoto
Period13/12/913/12/11

ASJC Scopus subject areas

  • Software

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  • Cite this

    Miyajima, T., Kuhara, T., Hanawa, T., Amano, H., & Boku, T. (2013). Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing. In FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology (pp. 466-469). [6718416] (FPT 2013 - Proceedings of the 2013 International Conference on Field Programmable Technology). https://doi.org/10.1109/FPT.2013.6718416