Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC

Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

The present paper focuses on applications that are periodic and have both latency and throughput constraints. For these applications, pipeline scheduling is effective for reducing energy consumption. Thus, the present paper proposes a pipelined task scheduling method for minimizing the energy consumption of GALS MP-SoC under latency and throughput constraints. First, we model target GALS MP-SoC architecture and application tasks. We then show that the energy optimization problem under this model belongs to the class of Mixed-Integer Linear Programming. Next, we propose a new scheduling method based on simulated annealing for the purpose of solving this problem quickly. Finally, experimental results demonstrate that the proposed method achieves a significant energy reduction on a real application under a practical architecture.

Original languageEnglish
Title of host publicationProceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
Pages797-802
Number of pages6
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, France
Duration: 2007 Apr 162007 Apr 20

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Conference

Conference2007 Design, Automation and Test in Europe Conference and Exhibition
Country/TerritoryFrance
CityNice Acropolis
Period07/4/1607/4/20

ASJC Scopus subject areas

  • Engineering(all)

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