The design and implementation of scalable deep neural network accelerator cores

Ryuichi Sakamoto; Ryo Takata; Jun Ishii; Masaaki Kondo; Hiroshi Nakamura; Tetsui Ohkubo; Takuya Kojima; Hideharu Amano

doi:10.1109/MCSoC.2017.29

The design and implementation of scalable deep neural network accelerator cores

Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embeddedsystems. Developing high-performance and power-efficient DNN engines becomesone of the important challenges for embedded systems. Since DNN algorithms orstructures are frequently updated, flexibility and performance scalability todeal with various types of networks are crucial requirement of the DNNaccelerator design. In this paper, we describe the architecture and LSI designof a flexible and scalable CNN accelerator called SNACC (Scalable NeuroAccelerator Core with Cubic integration) which consists of several processingcores, on-chip memory modules, and ThruChip Interface (TCI). We evaluate thescalability of SNACC with detailed simulation varying the number of cores andoff-chip memory access bandwidth. The results show that the energy efficiency of the accelerator becomes the highest in eight cores configuration with500MB/s off-chip bandwidth.

Original language	English
Title of host publication	Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	13-20
Number of pages	8
Volume	2018-January
ISBN (Electronic)	9781538634417
DOIs	https://doi.org/10.1109/MCSoC.2017.29
Publication status	Published - 2018 Mar 26
Event	11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 - Seoul, Korea, Republic of Duration: 2017 Sep 18 → 2017 Sep 20

Other

Other	11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017
Country	Korea, Republic of
City	Seoul
Period	17/9/18 → 17/9/20

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Keywords

3D-Integration
Accelerator
CNN
LSI Design

ASJC Scopus subject areas

Safety, Risk, Reliability and Quality
Hardware and Architecture
Signal Processing

Cite this

Sakamoto, R., Takata, R., Ishii, J., Kondo, M., Nakamura, H., Ohkubo, T., Kojima, T., & Amano, H. (2018). The design and implementation of scalable deep neural network accelerator cores. In Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 (Vol. 2018-January, pp. 13-20). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MCSoC.2017.29

The design and implementation of scalable deep neural network accelerator cores. / Sakamoto, Ryuichi; Takata, Ryo; Ishii, Jun; Kondo, Masaaki; Nakamura, Hiroshi; Ohkubo, Tetsui; Kojima, Takuya; Amano, Hideharu.

Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 13-20.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sakamoto, R, Takata, R, Ishii, J, Kondo, M, Nakamura, H, Ohkubo, T, Kojima, T & Amano, H 2018, The design and implementation of scalable deep neural network accelerator cores. in Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 13-20, 11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017, Seoul, Korea, Republic of, 17/9/18. https://doi.org/10.1109/MCSoC.2017.29

Sakamoto R, Takata R, Ishii J, Kondo M, Nakamura H, Ohkubo T et al. The design and implementation of scalable deep neural network accelerator cores. In Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 13-20 https://doi.org/10.1109/MCSoC.2017.29

Sakamoto, Ryuichi ; Takata, Ryo ; Ishii, Jun ; Kondo, Masaaki ; Nakamura, Hiroshi ; Ohkubo, Tetsui ; Kojima, Takuya ; Amano, Hideharu. / The design and implementation of scalable deep neural network accelerator cores. Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 13-20

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Access to Document

10.1109/MCSoC.2017.29