Abstract
Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embeddedsystems. Developing high-performance and power-efficient DNN engines becomesone of the important challenges for embedded systems. Since DNN algorithms orstructures are frequently updated, flexibility and performance scalability todeal with various types of networks are crucial requirement of the DNNaccelerator design. In this paper, we describe the architecture and LSI designof a flexible and scalable CNN accelerator called SNACC (Scalable NeuroAccelerator Core with Cubic integration) which consists of several processingcores, on-chip memory modules, and ThruChip Interface (TCI). We evaluate thescalability of SNACC with detailed simulation varying the number of cores andoff-chip memory access bandwidth. The results show that the energy efficiency of the accelerator becomes the highest in eight cores configuration with500MB/s off-chip bandwidth.
Original language | English |
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Title of host publication | Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 13-20 |
Number of pages | 8 |
Volume | 2018-January |
ISBN (Electronic) | 9781538634417 |
DOIs | |
Publication status | Published - 2018 Mar 26 |
Event | 11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 - Seoul, Korea, Republic of Duration: 2017 Sep 18 → 2017 Sep 20 |
Other
Other | 11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 |
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Country | Korea, Republic of |
City | Seoul |
Period | 17/9/18 → 17/9/20 |
Keywords
- 3D-Integration
- Accelerator
- CNN
- LSI Design
ASJC Scopus subject areas
- Safety, Risk, Reliability and Quality
- Hardware and Architecture
- Signal Processing