The design and implementation of scalable deep neural network accelerator cores

Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Due to the recent advances in Deep Neural Network (DNN) technologies, recognition and inference applications are expected to run on mobile embeddedsystems. Developing high-performance and power-efficient DNN engines becomesone of the important challenges for embedded systems. Since DNN algorithms orstructures are frequently updated, flexibility and performance scalability todeal with various types of networks are crucial requirement of the DNNaccelerator design. In this paper, we describe the architecture and LSI designof a flexible and scalable CNN accelerator called SNACC (Scalable NeuroAccelerator Core with Cubic integration) which consists of several processingcores, on-chip memory modules, and ThruChip Interface (TCI). We evaluate thescalability of SNACC with detailed simulation varying the number of cores andoff-chip memory access bandwidth. The results show that the energy efficiency of the accelerator becomes the highest in eight cores configuration with500MB/s off-chip bandwidth.

Original languageEnglish
Title of host publicationProceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages13-20
Number of pages8
Volume2018-January
ISBN (Electronic)9781538634417
DOIs
Publication statusPublished - 2018 Mar 26
Event11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 - Seoul, Korea, Republic of
Duration: 2017 Sep 182017 Sep 20

Other

Other11th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017
CountryKorea, Republic of
CitySeoul
Period17/9/1817/9/20

    Fingerprint

Keywords

  • 3D-Integration
  • Accelerator
  • CNN
  • LSI Design

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture
  • Signal Processing

Cite this

Sakamoto, R., Takata, R., Ishii, J., Kondo, M., Nakamura, H., Ohkubo, T., Kojima, T., & Amano, H. (2018). The design and implementation of scalable deep neural network accelerator cores. In Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 (Vol. 2018-January, pp. 13-20). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MCSoC.2017.29