The impact of routing cache on high-performance switches

Michihiro Koibuchi, Shin Ichi Ishida, Hiroaki Nishi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Large parallel applications become sensitive to communication latencies, suggesting the need for low-latency networks in high-performance computer systems. Switch delay dominates network latencies, especially for a large number of small transfer data. To reduce the network latencies, we exploit routing cache on a switch. Routing decision based on off-chip CAM(Content Addressable Memory)-based table lookup imposes a significant delay, however, using on-chip small routing cache can bypass it when it hits. Our simulation results showed that 1,024-entry routing cache improves not only up to 13% of packet latency but also up to 18% of network throughput compared with no-cache switches.

Original languageEnglish
Title of host publication10th International Conference on Optical Internet, COIN 2012
Pages40-41
Number of pages2
Publication statusPublished - 2012 Sep 28
Event10th International Conference on Optical Internet, COIN 2012 - Yokohama, Kanagawa, Japan
Duration: 2012 May 292012 May 31

Publication series

Name10th International Conference on Optical Internet, COIN 2012

Other

Other10th International Conference on Optical Internet, COIN 2012
CountryJapan
CityYokohama, Kanagawa
Period12/5/2912/5/31

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ASJC Scopus subject areas

  • Computer Networks and Communications

Cite this

Koibuchi, M., Ishida, S. I., & Nishi, H. (2012). The impact of routing cache on high-performance switches. In 10th International Conference on Optical Internet, COIN 2012 (pp. 40-41). [6245930] (10th International Conference on Optical Internet, COIN 2012).