TY - GEN
T1 - The Instruction Execution Mechanism for Responsive Multithreaded Processor
AU - Itou, Tstomu
AU - Yamasaki, Nobuyuki
N1 - Funding Information:
This study was performed through Special Coordination Funds of the Ministry of Education, Culture, Sports, Science and Technology of the Japanese Government.
Publisher Copyright:
Copyright © (2004) by the International Society for Computers and Their Applications. All rights reserved.
PY - 2004
Y1 - 2004
N2 - This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is controlled by using priority in RMT Processor. The highest priority thread is executed first in RMT Processor. Real-time applications, such as soft real-time processing including multimedia processing, require high computing performance. So we design the vector processing unit. Since multiple threads are executed in parallel by the multithreading architecture, these threads execute vector operations in parallel. We design the vector processing unit so that multiple threads are able to share vector registers and execute vector operations efficiently. Moreover, we design a vector compound execution mechanism to improve the performance of vector operations.
AB - This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is controlled by using priority in RMT Processor. The highest priority thread is executed first in RMT Processor. Real-time applications, such as soft real-time processing including multimedia processing, require high computing performance. So we design the vector processing unit. Since multiple threads are executed in parallel by the multithreading architecture, these threads execute vector operations in parallel. We design the vector processing unit so that multiple threads are able to share vector registers and execute vector operations efficiently. Moreover, we design a vector compound execution mechanism to improve the performance of vector operations.
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M3 - Conference contribution
AN - SCOPUS:60749101626
T3 - 19th International Conference on Computers and Their Applications 2004, CATA 2004
SP - 252
EP - 255
BT - 19th International Conference on Computers and Their Applications 2004, CATA 2004
A2 - Gupta, Bidyut
PB - The International Society for Computers and Their Applications (ISCA)
T2 - 19th International Conference on Computers and Their Applications, CATA 2004
Y2 - 18 March 2004 through 20 March 2004
ER -