The Instruction Execution Mechanism for Responsive Multithreaded Processor

Tstomu Itou, Nobuyuki Yamasaki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is controlled by using priority in RMT Processor. The highest priority thread is executed first in RMT Processor. Real-time applications, such as soft real-time processing including multimedia processing, require high computing performance. So we design the vector processing unit. Since multiple threads are executed in parallel by the multithreading architecture, these threads execute vector operations in parallel. We design the vector processing unit so that multiple threads are able to share vector registers and execute vector operations efficiently. Moreover, we design a vector compound execution mechanism to improve the performance of vector operations.

Original languageEnglish
Title of host publication19th International Conference on Computers and Their Applications 2004, CATA 2004
EditorsBidyut Gupta
PublisherThe International Society for Computers and Their Applications (ISCA)
Pages252-255
Number of pages4
ISBN (Electronic)9781618395511
Publication statusPublished - 2004
Event19th International Conference on Computers and Their Applications, CATA 2004 - Seattle, United States
Duration: 2004 Mar 182004 Mar 20

Publication series

Name19th International Conference on Computers and Their Applications 2004, CATA 2004

Conference

Conference19th International Conference on Computers and Their Applications, CATA 2004
Country/TerritoryUnited States
CitySeattle
Period04/3/1804/3/20

ASJC Scopus subject areas

  • Computer Science(all)

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