The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism)

Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, Hideharu Amano

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Two component architectures for MIN-connected multiprocessors: PBSF (the piled banyan switching fabrics) and MINC (MIN with cache consistency mechanism) are evaluated with a real machine SNAIL-2 and an instruction level simulator. The PBSF is a high bandwidth MIN with three dimensional structure, and the MINC is a mechanism for controlling the consistency of private cache modules located between processors and the MIN. Empirical implementation and simulation results show that the performance improvement of cache controlled by the MINC is significant, and throughput of the PBSF is sufficient if the cache is provided.

Original languageEnglish
Pages (from-to)352-370
Number of pages19
JournalParallel Computing
Volume31
Issue number3-4
DOIs
Publication statusPublished - 2005 Mar

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Multiprocessor
Cache
Simulators
Throughput
Bandwidth
Simulator
Sufficient
Module
Three-dimensional
Simulation

Keywords

  • Interconnection networks
  • Parallel architectures
  • Performance evaluation

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). / Midorikawa, Takashi; Shiraishi, Daisuke; Shigeno, Masayoshi; Tanabe, Yasuki; Hanawa, Toshihiro; Amano, Hideharu.

In: Parallel Computing, Vol. 31, No. 3-4, 03.2005, p. 352-370.

Research output: Contribution to journalArticle

Midorikawa, Takashi ; Shiraishi, Daisuke ; Shigeno, Masayoshi ; Tanabe, Yasuki ; Hanawa, Toshihiro ; Amano, Hideharu. / The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). In: Parallel Computing. 2005 ; Vol. 31, No. 3-4. pp. 352-370.
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