TY - GEN
T1 - The preliminary evaluation of MBP-light with two protocol policies for a massively parallel processor-JUMP-1
AU - Hiroaki, Inoue
AU - Anjo, Kenichiro
AU - Yamamoto, Junji
AU - Tanabe, Jun
AU - Wakabayashi, Masaki
AU - Sato, Mitsuru
AU - Amano, Hideharu
AU - Hiraki, Kei
N1 - Funding Information:
A part of this research was supported by the Grant-in-Aid for Scientific Research on Priority Areas, #04235130, from the Ministry of Education, Science and Culture. This research is also supported by Parallel and Distributed system Consosium.
Publisher Copyright:
© 1999 IEEE.
PY - 1999
Y1 - 1999
N2 - A massively parallel processor called JUMP-1 has been developed to build an efficient cache coherent-distributed shared memory (DSM) on a large system with more than 1000 processors. Here, the dedicated processor called MBP (Memory Based Processor)-light to manage the DSM of JUMP-1 is introduced, and its preliminary performance with two protocol policies-update/invalidate-is evaluated. From results of its simulation, it appears that simple operations like the tag check and the collection/generation of acknowledgment packets are mostly processed by the hardware mechanisms in MBP-light without the aids of the core processor with both policies. Also, the buffer-register architecture adopted by the core processor in MBP-light is exploited enough to process a protocol transaction for both policies.
AB - A massively parallel processor called JUMP-1 has been developed to build an efficient cache coherent-distributed shared memory (DSM) on a large system with more than 1000 processors. Here, the dedicated processor called MBP (Memory Based Processor)-light to manage the DSM of JUMP-1 is introduced, and its preliminary performance with two protocol policies-update/invalidate-is evaluated. From results of its simulation, it appears that simple operations like the tag check and the collection/generation of acknowledgment packets are mostly processed by the hardware mechanisms in MBP-light without the aids of the core processor with both policies. Also, the buffer-register architecture adopted by the core processor in MBP-light is exploited enough to process a protocol transaction for both policies.
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U2 - 10.1109/FMPC.1999.750609
DO - 10.1109/FMPC.1999.750609
M3 - Conference contribution
AN - SCOPUS:0004392913
T3 - Proceedings - Frontiers 1999, 7th Symposium on the Frontiers of Massively Parallel Computation
SP - 268
EP - 275
BT - Proceedings - Frontiers 1999, 7th Symposium on the Frontiers of Massively Parallel Computation
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th Symposium on the Frontiers of Massively Parallel Computation, Frontiers 1999
Y2 - 21 February 1999 through 25 February 1999
ER -
