The preliminary evaluation of MBP-light with two protocol policies for a massively parallel processor-JUMP-1

Inoue Hiroaki, Kenichiro Anjo, Junji Yamamoto, Jun Tanabe, Masaki Wakabayashi, Mitsuru Sato, Hideharu Amano, Kei Hiraki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A massively parallel processor called JUMP-1 has been developed to build an efficient cache coherent-distributed shared memory (DSM) on a large system with more than 1000 processors. Here, the dedicated processor called MBP (Memory Based Processor)-light to manage the DSM of JUMP-1 is introduced, and its preliminary performance with two protocol policies-update/invalidate-is evaluated. From results of its simulation, it appears that simple operations like the tag check and the collection/generation of acknowledgment packets are mostly processed by the hardware mechanisms in MBP-light without the aids of the core processor with both policies. Also, the buffer-register architecture adopted by the core processor in MBP-light is exploited enough to process a protocol transaction for both policies.

Original languageEnglish
Title of host publicationProceedings - Frontiers 1999, 7th Symposium on the Frontiers of Massively Parallel Computation
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages268-275
Number of pages8
ISBN (Electronic)0769500870, 9780769500874
DOIs
Publication statusPublished - 1999
Event7th Symposium on the Frontiers of Massively Parallel Computation, Frontiers 1999 - Annapolis, United States
Duration: 1999 Feb 211999 Feb 25

Publication series

NameProceedings - Frontiers 1999, 7th Symposium on the Frontiers of Massively Parallel Computation

Other

Other7th Symposium on the Frontiers of Massively Parallel Computation, Frontiers 1999
CountryUnited States
CityAnnapolis
Period99/2/2199/2/25

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Modelling and Simulation

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