Thermal-aware CMOS: Challenges for future technology and design evolutions

Ken Uchida, Tsunaki Takahashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Three-dimensional (3D) field-effect transistors (FETs) such as FinFETs and nanowire FETs are device structures for extremely scaled FETs. However, the thermal properties of 3D FETs become worse than those of conventional planar MOSFETs. As a result, an increase in channel temperature during operation, which is called self-heating effects (SHEs) is prominent in nanoscale devices. In this work, 1) SHEs in scaled devices are experimentally evaluated. In particular, SHEs of SOI devices with ultra-thin (UT) buried oxide (BOX) are measured using a four-terminal gate electrode. Then, the modeling of thermal resistance/conductance of interconnect wires are discussed. Finally, the co-optimization of thermal and electrical properties of devices in terms of analog performance is described.

Original languageEnglish
Title of host publication2016 46th European Solid-State Device Research Conference, ESSDERC 2016
PublisherEditions Frontieres
Pages150-153
Number of pages4
Volume2016-October
ISBN (Electronic)9781509029693
DOIs
Publication statusPublished - 2016 Oct 18
Event46th European Solid-State Device Research Conference, ESSDERC 2016 - Lausanne, Switzerland
Duration: 2016 Sep 122016 Sep 15

Other

Other46th European Solid-State Device Research Conference, ESSDERC 2016
CountrySwitzerland
CityLausanne
Period16/9/1216/9/15

Fingerprint

Field effect transistors
Heating
Thermodynamic properties
Heat resistance
Nanowires
Electric properties
Wire
Electrodes
Oxides
Hot Temperature
Temperature

Keywords

  • fin-type FETs
  • Joule heating
  • nanowire FETs
  • slef-heating
  • SOI
  • thermal resistance

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Uchida, K., & Takahashi, T. (2016). Thermal-aware CMOS: Challenges for future technology and design evolutions. In 2016 46th European Solid-State Device Research Conference, ESSDERC 2016 (Vol. 2016-October, pp. 150-153). [7599609] Editions Frontieres. https://doi.org/10.1109/ESSDERC.2016.7599609

Thermal-aware CMOS : Challenges for future technology and design evolutions. / Uchida, Ken; Takahashi, Tsunaki.

2016 46th European Solid-State Device Research Conference, ESSDERC 2016. Vol. 2016-October Editions Frontieres, 2016. p. 150-153 7599609.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Uchida, K & Takahashi, T 2016, Thermal-aware CMOS: Challenges for future technology and design evolutions. in 2016 46th European Solid-State Device Research Conference, ESSDERC 2016. vol. 2016-October, 7599609, Editions Frontieres, pp. 150-153, 46th European Solid-State Device Research Conference, ESSDERC 2016, Lausanne, Switzerland, 16/9/12. https://doi.org/10.1109/ESSDERC.2016.7599609
Uchida K, Takahashi T. Thermal-aware CMOS: Challenges for future technology and design evolutions. In 2016 46th European Solid-State Device Research Conference, ESSDERC 2016. Vol. 2016-October. Editions Frontieres. 2016. p. 150-153. 7599609 https://doi.org/10.1109/ESSDERC.2016.7599609
Uchida, Ken ; Takahashi, Tsunaki. / Thermal-aware CMOS : Challenges for future technology and design evolutions. 2016 46th European Solid-State Device Research Conference, ESSDERC 2016. Vol. 2016-October Editions Frontieres, 2016. pp. 150-153
@inproceedings{7cc986a5c23744b19c0ea1dd5daa384d,
title = "Thermal-aware CMOS: Challenges for future technology and design evolutions",
abstract = "Three-dimensional (3D) field-effect transistors (FETs) such as FinFETs and nanowire FETs are device structures for extremely scaled FETs. However, the thermal properties of 3D FETs become worse than those of conventional planar MOSFETs. As a result, an increase in channel temperature during operation, which is called self-heating effects (SHEs) is prominent in nanoscale devices. In this work, 1) SHEs in scaled devices are experimentally evaluated. In particular, SHEs of SOI devices with ultra-thin (UT) buried oxide (BOX) are measured using a four-terminal gate electrode. Then, the modeling of thermal resistance/conductance of interconnect wires are discussed. Finally, the co-optimization of thermal and electrical properties of devices in terms of analog performance is described.",
keywords = "fin-type FETs, Joule heating, nanowire FETs, slef-heating, SOI, thermal resistance",
author = "Ken Uchida and Tsunaki Takahashi",
year = "2016",
month = "10",
day = "18",
doi = "10.1109/ESSDERC.2016.7599609",
language = "English",
volume = "2016-October",
pages = "150--153",
booktitle = "2016 46th European Solid-State Device Research Conference, ESSDERC 2016",
publisher = "Editions Frontieres",

}

TY - GEN

T1 - Thermal-aware CMOS

T2 - Challenges for future technology and design evolutions

AU - Uchida, Ken

AU - Takahashi, Tsunaki

PY - 2016/10/18

Y1 - 2016/10/18

N2 - Three-dimensional (3D) field-effect transistors (FETs) such as FinFETs and nanowire FETs are device structures for extremely scaled FETs. However, the thermal properties of 3D FETs become worse than those of conventional planar MOSFETs. As a result, an increase in channel temperature during operation, which is called self-heating effects (SHEs) is prominent in nanoscale devices. In this work, 1) SHEs in scaled devices are experimentally evaluated. In particular, SHEs of SOI devices with ultra-thin (UT) buried oxide (BOX) are measured using a four-terminal gate electrode. Then, the modeling of thermal resistance/conductance of interconnect wires are discussed. Finally, the co-optimization of thermal and electrical properties of devices in terms of analog performance is described.

AB - Three-dimensional (3D) field-effect transistors (FETs) such as FinFETs and nanowire FETs are device structures for extremely scaled FETs. However, the thermal properties of 3D FETs become worse than those of conventional planar MOSFETs. As a result, an increase in channel temperature during operation, which is called self-heating effects (SHEs) is prominent in nanoscale devices. In this work, 1) SHEs in scaled devices are experimentally evaluated. In particular, SHEs of SOI devices with ultra-thin (UT) buried oxide (BOX) are measured using a four-terminal gate electrode. Then, the modeling of thermal resistance/conductance of interconnect wires are discussed. Finally, the co-optimization of thermal and electrical properties of devices in terms of analog performance is described.

KW - fin-type FETs

KW - Joule heating

KW - nanowire FETs

KW - slef-heating

KW - SOI

KW - thermal resistance

UR - http://www.scopus.com/inward/record.url?scp=84994443302&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84994443302&partnerID=8YFLogxK

U2 - 10.1109/ESSDERC.2016.7599609

DO - 10.1109/ESSDERC.2016.7599609

M3 - Conference contribution

AN - SCOPUS:84994443302

VL - 2016-October

SP - 150

EP - 153

BT - 2016 46th European Solid-State Device Research Conference, ESSDERC 2016

PB - Editions Frontieres

ER -