@inproceedings{7cc986a5c23744b19c0ea1dd5daa384d,
title = "Thermal-aware CMOS: Challenges for future technology and design evolutions",
abstract = "Three-dimensional (3D) field-effect transistors (FETs) such as FinFETs and nanowire FETs are device structures for extremely scaled FETs. However, the thermal properties of 3D FETs become worse than those of conventional planar MOSFETs. As a result, an increase in channel temperature during operation, which is called self-heating effects (SHEs) is prominent in nanoscale devices. In this work, 1) SHEs in scaled devices are experimentally evaluated. In particular, SHEs of SOI devices with ultra-thin (UT) buried oxide (BOX) are measured using a four-terminal gate electrode. Then, the modeling of thermal resistance/conductance of interconnect wires are discussed. Finally, the co-optimization of thermal and electrical properties of devices in terms of analog performance is described.",
keywords = "Joule heating, SOI, fin-type FETs, nanowire FETs, slef-heating, thermal resistance",
author = "Ken Uchida and Tsunaki Takahashi",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 46th European Solid-State Device Research Conference, ESSDERC 2016 ; Conference date: 12-09-2016 Through 15-09-2016",
year = "2016",
month = oct,
day = "18",
doi = "10.1109/ESSDERC.2016.7599609",
language = "English",
series = "European Solid-State Device Research Conference",
publisher = "Editions Frontieres",
pages = "150--153",
booktitle = "2016 46th European Solid-State Device Research Conference, ESSDERC 2016",
}