Thermal stress analysis under thermal cycling test for SiC power device heat dissipation structures using Ag sintered layer

Kensuke Osonoe, Masaaki Aoki, Akihiro Mochizuki, Yoshio Murakami, Hitoshi Kida, Goro Yoshinari, Nobuhiko Nakano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We have analyzed 3D thermal stress profile under TCT using multi-physics solver for SiC power device heat dissipation structures with a direct chip bonding on Cu plate by Ag sintered layer. The results showed that the maximum stress value in SiC chip structure is higher than that in Si chip structure. This is because Young's modulus of SiC is higher than that of Si. The maximum stress point is at the corner of Ag sintered bonding layer for both SiC/Si structures. This bonding layer corner value increases as Cu plate thickness becomes thicker. It was also found that at Ag sintered layer center von Mises stress and the shear stress are almost the same, and at Ag sintered layer corner the normal stress is major component of von Mises stress.

Original languageEnglish
Title of host publication2017 International Conference on Electronics Packaging, ICEP 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages544-548
Number of pages5
ISBN (Electronic)9784990218836
DOIs
Publication statusPublished - 2017 Jun 5
Event2017 International Conference on Electronics Packaging, ICEP 2017 - Tendo, Yamagata, Japan
Duration: 2017 Apr 192017 Apr 22

Other

Other2017 International Conference on Electronics Packaging, ICEP 2017
CountryJapan
CityTendo, Yamagata
Period17/4/1917/4/22

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Keywords

  • Ag sintering chip-attachment
  • anisotropic material parameter
  • multi-physics solver
  • power semiconductor devices
  • SiC chip system
  • stress and strain analysis

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Osonoe, K., Aoki, M., Mochizuki, A., Murakami, Y., Kida, H., Yoshinari, G., & Nakano, N. (2017). Thermal stress analysis under thermal cycling test for SiC power device heat dissipation structures using Ag sintered layer. In 2017 International Conference on Electronics Packaging, ICEP 2017 (pp. 544-548). [7939443] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/ICEP.2017.7939443