Third-order phase-locked loops using dual loops with improved stability

Minoru Kamata, Takashi Shono, Takahiko Saba, Iwao Sasase, Shinsaku Mori

Research output: Contribution to conferencePaper

7 Citations (Scopus)

Abstract

A third-order PLL has an instability problem. It is known that the system of dual loops improves the instability and suppresses a steady-state error of the third-order PLL. A conventional third-order PLL using dual loops is implemented by digital equipment. Since the digital PLL cannot be used at high frequency band in satellite communications because of limitation of the operational frequency, the conventional third-order PLL using dual loops are unavailable such an environment. In this paper, we propose a new third-order PLL using dual loops which are implemented by analog equipment. We investigate the transient response and the steady-state behavior of the proposed PLL due to the frequency ramp transition. Results show the steady-state phase error of the proposed PLL is suppressed. Furthermore, we show the stability of the proposed PLL is better than that of the typical third-order PLL.

Original languageEnglish
Pages338-341
Number of pages4
Publication statusPublished - 1997 Dec 1
EventProceedings of the 1997 6th IEEE Pacific Rim Conference on Communications, Computers and Signal Processing. Part 1 (of 2) - Victoria, Can
Duration: 1997 Aug 201997 Aug 22

Other

OtherProceedings of the 1997 6th IEEE Pacific Rim Conference on Communications, Computers and Signal Processing. Part 1 (of 2)
CityVictoria, Can
Period97/8/2097/8/22

ASJC Scopus subject areas

  • Signal Processing
  • Computer Networks and Communications

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    Kamata, M., Shono, T., Saba, T., Sasase, I., & Mori, S. (1997). Third-order phase-locked loops using dual loops with improved stability. 338-341. Paper presented at Proceedings of the 1997 6th IEEE Pacific Rim Conference on Communications, Computers and Signal Processing. Part 1 (of 2), Victoria, Can, .