Three-dimensional layout of on-chip tree-based networks

Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

Three-dimensional Network-on-Chip (3-D NoC) is an emerging research area exploring the network architecture of 3-D ICs that stack several smaller wafers or dice for reducing wire length and wire delay. Various network topologies such as meshes, tori, and trees have been used for NoCs. In particular, much attention has been focused on tree-based topologies, such as Fat Trees and Fat H- Tree, because of their relatively short hop-count that enables lower latency communication compared to meshes or tori. However, since on-chip tree-based networks in their 2-D layouts have long wire links around the root, they generate serious wire delay, posing severe problems to modern VLSI design. In this paper, we propose a 3-D layout scheme of trees including Fat Trees and Fat H- Tree for 3-D ICs in order to resolve the trees' intrinsic disadvantage. The 3-D layouts are compared with the original 2-D layouts in terms of network logic area, wire length, wire delay, number of repeaters inserted, and energy consumption. Evaluation results show that 1) total wire length is reduced by 25.0% to 50.0%; 2) wire delay is improved and repeater buffers that consume considerable energy can be removed; 3) flit transmission energy is reduced by up to 47.0%; 4) area overhead is at most 7.8%, which compares favorably to those for 3-D mesh and torus.

Original languageEnglish
Title of host publicationProceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN
Pages281-288
Number of pages8
DOIs
Publication statusPublished - 2008
Event9th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2008 - Sydney, NSW, Australia
Duration: 2008 May 72008 May 9

Other

Other9th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2008
CountryAustralia
CitySydney, NSW
Period08/5/708/5/9

Fingerprint

Wire
Oils and fats
Telecommunication repeaters
Topology
Network architecture
Energy utilization
Communication
Network-on-chip

ASJC Scopus subject areas

  • Computer Science(all)

Cite this

Matsutani, H., Koibuchi, M., Hsu, D. F., & Amano, H. (2008). Three-dimensional layout of on-chip tree-based networks. In Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN (pp. 281-288). [4520228] https://doi.org/10.1109/I-SPAN.2008.39

Three-dimensional layout of on-chip tree-based networks. / Matsutani, Hiroki; Koibuchi, Michihiro; Hsu, D. Frank; Amano, Hideharu.

Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN. 2008. p. 281-288 4520228.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Matsutani, H, Koibuchi, M, Hsu, DF & Amano, H 2008, Three-dimensional layout of on-chip tree-based networks. in Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN., 4520228, pp. 281-288, 9th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2008, Sydney, NSW, Australia, 08/5/7. https://doi.org/10.1109/I-SPAN.2008.39
Matsutani H, Koibuchi M, Hsu DF, Amano H. Three-dimensional layout of on-chip tree-based networks. In Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN. 2008. p. 281-288. 4520228 https://doi.org/10.1109/I-SPAN.2008.39
Matsutani, Hiroki ; Koibuchi, Michihiro ; Hsu, D. Frank ; Amano, Hideharu. / Three-dimensional layout of on-chip tree-based networks. Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN. 2008. pp. 281-288
@inproceedings{ad47f00fb77c481c820ac17a927a7494,
title = "Three-dimensional layout of on-chip tree-based networks",
abstract = "Three-dimensional Network-on-Chip (3-D NoC) is an emerging research area exploring the network architecture of 3-D ICs that stack several smaller wafers or dice for reducing wire length and wire delay. Various network topologies such as meshes, tori, and trees have been used for NoCs. In particular, much attention has been focused on tree-based topologies, such as Fat Trees and Fat H- Tree, because of their relatively short hop-count that enables lower latency communication compared to meshes or tori. However, since on-chip tree-based networks in their 2-D layouts have long wire links around the root, they generate serious wire delay, posing severe problems to modern VLSI design. In this paper, we propose a 3-D layout scheme of trees including Fat Trees and Fat H- Tree for 3-D ICs in order to resolve the trees' intrinsic disadvantage. The 3-D layouts are compared with the original 2-D layouts in terms of network logic area, wire length, wire delay, number of repeaters inserted, and energy consumption. Evaluation results show that 1) total wire length is reduced by 25.0{\%} to 50.0{\%}; 2) wire delay is improved and repeater buffers that consume considerable energy can be removed; 3) flit transmission energy is reduced by up to 47.0{\%}; 4) area overhead is at most 7.8{\%}, which compares favorably to those for 3-D mesh and torus.",
author = "Hiroki Matsutani and Michihiro Koibuchi and Hsu, {D. Frank} and Hideharu Amano",
year = "2008",
doi = "10.1109/I-SPAN.2008.39",
language = "English",
isbn = "9780769531250",
pages = "281--288",
booktitle = "Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN",

}

TY - GEN

T1 - Three-dimensional layout of on-chip tree-based networks

AU - Matsutani, Hiroki

AU - Koibuchi, Michihiro

AU - Hsu, D. Frank

AU - Amano, Hideharu

PY - 2008

Y1 - 2008

N2 - Three-dimensional Network-on-Chip (3-D NoC) is an emerging research area exploring the network architecture of 3-D ICs that stack several smaller wafers or dice for reducing wire length and wire delay. Various network topologies such as meshes, tori, and trees have been used for NoCs. In particular, much attention has been focused on tree-based topologies, such as Fat Trees and Fat H- Tree, because of their relatively short hop-count that enables lower latency communication compared to meshes or tori. However, since on-chip tree-based networks in their 2-D layouts have long wire links around the root, they generate serious wire delay, posing severe problems to modern VLSI design. In this paper, we propose a 3-D layout scheme of trees including Fat Trees and Fat H- Tree for 3-D ICs in order to resolve the trees' intrinsic disadvantage. The 3-D layouts are compared with the original 2-D layouts in terms of network logic area, wire length, wire delay, number of repeaters inserted, and energy consumption. Evaluation results show that 1) total wire length is reduced by 25.0% to 50.0%; 2) wire delay is improved and repeater buffers that consume considerable energy can be removed; 3) flit transmission energy is reduced by up to 47.0%; 4) area overhead is at most 7.8%, which compares favorably to those for 3-D mesh and torus.

AB - Three-dimensional Network-on-Chip (3-D NoC) is an emerging research area exploring the network architecture of 3-D ICs that stack several smaller wafers or dice for reducing wire length and wire delay. Various network topologies such as meshes, tori, and trees have been used for NoCs. In particular, much attention has been focused on tree-based topologies, such as Fat Trees and Fat H- Tree, because of their relatively short hop-count that enables lower latency communication compared to meshes or tori. However, since on-chip tree-based networks in their 2-D layouts have long wire links around the root, they generate serious wire delay, posing severe problems to modern VLSI design. In this paper, we propose a 3-D layout scheme of trees including Fat Trees and Fat H- Tree for 3-D ICs in order to resolve the trees' intrinsic disadvantage. The 3-D layouts are compared with the original 2-D layouts in terms of network logic area, wire length, wire delay, number of repeaters inserted, and energy consumption. Evaluation results show that 1) total wire length is reduced by 25.0% to 50.0%; 2) wire delay is improved and repeater buffers that consume considerable energy can be removed; 3) flit transmission energy is reduced by up to 47.0%; 4) area overhead is at most 7.8%, which compares favorably to those for 3-D mesh and torus.

UR - http://www.scopus.com/inward/record.url?scp=49149099231&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=49149099231&partnerID=8YFLogxK

U2 - 10.1109/I-SPAN.2008.39

DO - 10.1109/I-SPAN.2008.39

M3 - Conference contribution

AN - SCOPUS:49149099231

SN - 9780769531250

SP - 281

EP - 288

BT - Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN

ER -