TY - GEN
T1 - Three-dimensional packaging structure for 3D-NoC
AU - Wada, Kikuo
AU - Hino, Shigekazu
AU - Yamasaki, Nobuyuki
PY - 2013/12/1
Y1 - 2013/12/1
N2 - In this paper, we propose a novel three-dimensional (3D) packaging structure for a network-on-chip (NoC) based a 3D system-on-chip (SoC). Our SiP is implemented by vertically connecting two homogeneous SoCs through an organic interposer; that is, two homogeneous SoCs are bonded face-to-face above and below the organic interposer. NoCs have routing capability that can communicate with each other even if opposing nodes are connected to different node pins, which enables high-speed communication between SoCs using low voltage and current. As the power supply and external I/O pins are implemented via the organic interposer, we performed simulations to assess power integrity (PI) and signal integrity (SI) compared to a conventional package. To assess vertical communication performance as a 3D package, we simulated high-speed characteristics using the organic interposer and through silicon vias (TSVs), and confirmed the superior performance of the organic interposer.
AB - In this paper, we propose a novel three-dimensional (3D) packaging structure for a network-on-chip (NoC) based a 3D system-on-chip (SoC). Our SiP is implemented by vertically connecting two homogeneous SoCs through an organic interposer; that is, two homogeneous SoCs are bonded face-to-face above and below the organic interposer. NoCs have routing capability that can communicate with each other even if opposing nodes are connected to different node pins, which enables high-speed communication between SoCs using low voltage and current. As the power supply and external I/O pins are implemented via the organic interposer, we performed simulations to assess power integrity (PI) and signal integrity (SI) compared to a conventional package. To assess vertical communication performance as a 3D package, we simulated high-speed characteristics using the organic interposer and through silicon vias (TSVs), and confirmed the superior performance of the organic interposer.
KW - 3D-LSI
KW - 3D-SiP
KW - FFCSP
KW - NoC
UR - http://www.scopus.com/inward/record.url?scp=84894190327&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84894190327&partnerID=8YFLogxK
U2 - 10.1109/EDAPS.2013.6724392
DO - 10.1109/EDAPS.2013.6724392
M3 - Conference contribution
AN - SCOPUS:84894190327
SN - 9781479923113
T3 - EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
SP - 72
EP - 75
BT - EDAPS 2013 - 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium
T2 - 2013 6th IEEE Electrical Design of Advanced Packaging Systems Symposium, EDAPS 2013
Y2 - 12 December 2013 through 15 December 2013
ER -