Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction

Masumi Saitoh, Akio Kaneko, Kimitoshi Okano, Tomoko Kinoshita, Satoshi Inaba, Yoshiaki Toyoshima, Ken Uchida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)

Abstract

In this paper, the first systematic study of uniaxial stress effects on mobility (μ)/on-current (Ion) enhancement and gate current (I g) reduction in FinFETs is described. We demonstrate for the first time that Ig of (110) side-surface pFinFETs is largely reduced by longitudinal compressive stress due to out-of-plane mass increase. (110) n/pFinFETs are superior to (100) FinFETs in terms of higher μ/Ion enhancement ratio by longitudinal strain and comparable/ higher short-channel Idsat. Three-dimensional stress design in FinFETs including transverse and vertical stresses is proposed based on the understanding of stress effects beyond bulk piezoresistance.

Original languageEnglish
Title of host publicationDigest of Technical Papers - Symposium on VLSI Technology
Pages18-19
Number of pages2
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT - Honolulu, HI, United States
Duration: 2008 Jun 172008 Jun 19

Other

Other2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT
CountryUnited States
CityHonolulu, HI
Period08/6/1708/6/19

Fingerprint

Ions
Compressive stress
FinFET

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Saitoh, M., Kaneko, A., Okano, K., Kinoshita, T., Inaba, S., Toyoshima, Y., & Uchida, K. (2008). Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction. In Digest of Technical Papers - Symposium on VLSI Technology (pp. 18-19). [4588547] https://doi.org/10.1109/VLSIT.2008.4588547

Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction. / Saitoh, Masumi; Kaneko, Akio; Okano, Kimitoshi; Kinoshita, Tomoko; Inaba, Satoshi; Toyoshima, Yoshiaki; Uchida, Ken.

Digest of Technical Papers - Symposium on VLSI Technology. 2008. p. 18-19 4588547.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Saitoh, M, Kaneko, A, Okano, K, Kinoshita, T, Inaba, S, Toyoshima, Y & Uchida, K 2008, Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction. in Digest of Technical Papers - Symposium on VLSI Technology., 4588547, pp. 18-19, 2008 Symposium on VLSI Technology Digest of Technical Papers, VLSIT, Honolulu, HI, United States, 08/6/17. https://doi.org/10.1109/VLSIT.2008.4588547
Saitoh M, Kaneko A, Okano K, Kinoshita T, Inaba S, Toyoshima Y et al. Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction. In Digest of Technical Papers - Symposium on VLSI Technology. 2008. p. 18-19. 4588547 https://doi.org/10.1109/VLSIT.2008.4588547
Saitoh, Masumi ; Kaneko, Akio ; Okano, Kimitoshi ; Kinoshita, Tomoko ; Inaba, Satoshi ; Toyoshima, Yoshiaki ; Uchida, Ken. / Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction. Digest of Technical Papers - Symposium on VLSI Technology. 2008. pp. 18-19
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