Threshold-voltage control schemes through substrate-bias for low-power high-speed CMOS LSI design

Tadahiro Kuroda, Takayasu Sakurai

Research output: Contribution to journalArticle

17 Citations (Scopus)

Abstract

Lowering supply voltage, VDD> is the most effective means to reduce power dissipation of CMOS LSI design. In low VDD, however, circuit delay increases and chip performance degrades. There are two means to maintain the chip performance: 1) to lower the threshold voltage, V th, to recover circuit speed, or 2) to introduce parallel and/or pipeline architectures to make up for slow device speed. The first approach increases standby power dissipation due to low Vth, while the second approach degrades worst case circuit speed caused by Vth fluctuation in low VDD. This paper presents two circuit techniques to solve these problems, in both of which Vth is controlled through substrate bias. A Standby Power Reduction (SPR) scheme raises Vth in a standby mode by applying substrate bias with a voltage-switch circuit. A Self-Adjusting Threshold-Voltage (SAT) scheme reduces Vth fluctuation in an active mode by adjusting substrate bias with a feed-back control circuit. Test chips are fabricated and effectiveness of the circuit techniques is examined. The SPR scheme reduces 50% of the active power dissipation while maintaining the speed and the standby power dissipation. The SAT scheme improves worst case circuit speed by a factor of 3 under a 1 V VDD.

Original languageEnglish
Pages (from-to)191-201
Number of pages11
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume13
Issue number2-3
Publication statusPublished - 1996
Externally publishedYes

Fingerprint

Threshold voltage
Voltage control
High Speed
Voltage
Substrate
Networks (circuits)
Substrates
Energy dissipation
Dissipation
Chip
Delay circuits
Fluctuations
Electric potential
Design
Feedback control
Feedback Control
Pipelines
Switches
Switch

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Information Systems
  • Signal Processing
  • Hardware and Architecture
  • Theoretical Computer Science

Cite this

@article{cfe5e844e247444db0a3304019041eb1,
title = "Threshold-voltage control schemes through substrate-bias for low-power high-speed CMOS LSI design",
abstract = "Lowering supply voltage, VDD> is the most effective means to reduce power dissipation of CMOS LSI design. In low VDD, however, circuit delay increases and chip performance degrades. There are two means to maintain the chip performance: 1) to lower the threshold voltage, V th, to recover circuit speed, or 2) to introduce parallel and/or pipeline architectures to make up for slow device speed. The first approach increases standby power dissipation due to low Vth, while the second approach degrades worst case circuit speed caused by Vth fluctuation in low VDD. This paper presents two circuit techniques to solve these problems, in both of which Vth is controlled through substrate bias. A Standby Power Reduction (SPR) scheme raises Vth in a standby mode by applying substrate bias with a voltage-switch circuit. A Self-Adjusting Threshold-Voltage (SAT) scheme reduces Vth fluctuation in an active mode by adjusting substrate bias with a feed-back control circuit. Test chips are fabricated and effectiveness of the circuit techniques is examined. The SPR scheme reduces 50{\%} of the active power dissipation while maintaining the speed and the standby power dissipation. The SAT scheme improves worst case circuit speed by a factor of 3 under a 1 V VDD.",
author = "Tadahiro Kuroda and Takayasu Sakurai",
year = "1996",
language = "English",
volume = "13",
pages = "191--201",
journal = "Journal of Signal Processing Systems",
issn = "1939-8018",
publisher = "Springer New York",
number = "2-3",

}

TY - JOUR

T1 - Threshold-voltage control schemes through substrate-bias for low-power high-speed CMOS LSI design

AU - Kuroda, Tadahiro

AU - Sakurai, Takayasu

PY - 1996

Y1 - 1996

N2 - Lowering supply voltage, VDD> is the most effective means to reduce power dissipation of CMOS LSI design. In low VDD, however, circuit delay increases and chip performance degrades. There are two means to maintain the chip performance: 1) to lower the threshold voltage, V th, to recover circuit speed, or 2) to introduce parallel and/or pipeline architectures to make up for slow device speed. The first approach increases standby power dissipation due to low Vth, while the second approach degrades worst case circuit speed caused by Vth fluctuation in low VDD. This paper presents two circuit techniques to solve these problems, in both of which Vth is controlled through substrate bias. A Standby Power Reduction (SPR) scheme raises Vth in a standby mode by applying substrate bias with a voltage-switch circuit. A Self-Adjusting Threshold-Voltage (SAT) scheme reduces Vth fluctuation in an active mode by adjusting substrate bias with a feed-back control circuit. Test chips are fabricated and effectiveness of the circuit techniques is examined. The SPR scheme reduces 50% of the active power dissipation while maintaining the speed and the standby power dissipation. The SAT scheme improves worst case circuit speed by a factor of 3 under a 1 V VDD.

AB - Lowering supply voltage, VDD> is the most effective means to reduce power dissipation of CMOS LSI design. In low VDD, however, circuit delay increases and chip performance degrades. There are two means to maintain the chip performance: 1) to lower the threshold voltage, V th, to recover circuit speed, or 2) to introduce parallel and/or pipeline architectures to make up for slow device speed. The first approach increases standby power dissipation due to low Vth, while the second approach degrades worst case circuit speed caused by Vth fluctuation in low VDD. This paper presents two circuit techniques to solve these problems, in both of which Vth is controlled through substrate bias. A Standby Power Reduction (SPR) scheme raises Vth in a standby mode by applying substrate bias with a voltage-switch circuit. A Self-Adjusting Threshold-Voltage (SAT) scheme reduces Vth fluctuation in an active mode by adjusting substrate bias with a feed-back control circuit. Test chips are fabricated and effectiveness of the circuit techniques is examined. The SPR scheme reduces 50% of the active power dissipation while maintaining the speed and the standby power dissipation. The SAT scheme improves worst case circuit speed by a factor of 3 under a 1 V VDD.

UR - http://www.scopus.com/inward/record.url?scp=0030205943&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030205943&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0030205943

VL - 13

SP - 191

EP - 201

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 2-3

ER -