Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs

Kensuke Ota; Masumi Saitoh; Yukio Nakabayashi; Takamitsu Ishihara; Toshinori Numata; Ken Uchida

doi:10.1109/ESSDERC.2010.5618447

Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs

Kensuke Ota, Masumi Saitoh, Yukio Nakabayashi, Takamitsu Ishihara, Toshinori Numata, Ken Uchida

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

Threshold voltage shift and drain current degradation by NBT stress in Si (100) and (110) pMOSFETs are systematically studied. Threshold voltage shift in (110) pFET is larger than that in (100) pFET. However, time and temperature dependence of NBTI suggest that the mechanisms of the NBTI degradation are independent of the surface orientations. It is newly found that the drain current degradation in (110) pFET is severer than that in (100) pFET even when the same amount of charges at the interface is generated. This can be explained by larger mobility degradation in (110) pFETs due to the generated interface traps.

Original language	English
Title of host publication	2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010
Pages	134-137
Number of pages	4
DOIs	https://doi.org/10.1109/ESSDERC.2010.5618447
Publication status	Published - 2010 Dec 15
Event	2010 European Solid State Device Research Conference, ESSDERC 2010 - Sevilla, Spain Duration: 2010 Sept 14 → 2010 Sept 16

Publication series

Name	2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010

Other

Other	2010 European Solid State Device Research Conference, ESSDERC 2010
Country/Territory	Spain
City	Sevilla
Period	10/9/14 → 10/9/16

ASJC Scopus subject areas

Condensed Matter Physics

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10.1109/ESSDERC.2010.5618447

Cite this

Ota, K., Saitoh, M., Nakabayashi, Y., Ishihara, T., Numata, T., & Uchida, K. (2010). Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs. In 2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010 (pp. 134-137). [5618447] (2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010). https://doi.org/10.1109/ESSDERC.2010.5618447

Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs. / Ota, Kensuke; Saitoh, Masumi; Nakabayashi, Yukio et al.
2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010. 2010. p. 134-137 5618447 (2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ota, K, Saitoh, M, Nakabayashi, Y, Ishihara, T, Numata, T & Uchida, K 2010, Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs. in 2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010., 5618447, 2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010, pp. 134-137, 2010 European Solid State Device Research Conference, ESSDERC 2010, Sevilla, Spain, 10/9/14. https://doi.org/10.1109/ESSDERC.2010.5618447

Ota K, Saitoh M, Nakabayashi Y, Ishihara T, Numata T, Uchida K. Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs. In 2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010. 2010. p. 134-137. 5618447. (2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010). doi: 10.1109/ESSDERC.2010.5618447

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Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs

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