Threshold voltage shift and drain current degradation by negative bias temperature instability in Si (110) p-channel metal-oxide-semiconductor field-effect transistor

K. Ota, M. Saitoh, Y. Nakabayashi, T. Ishihara, Ken Uchida, T. Numata

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

Negative bias temperature instability in Si (100) and (110) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) is systematically studied. Threshold voltage shift in (110) pMOSFETs is found to be larger than that in (100) pMOSFETs because of larger amount of the generated interface traps. On the other hand, mechanisms behind the generation of the interface traps are independent of the surface orientations. We newly found that drain current degradation in (110) pMOSFETs is severer than that in (100) pMOSFETs even when the same amount of charges is generated at the interface. This can be explained by larger mobility degradation in (110) pMOSFETs.

Original languageEnglish
Article number212109
JournalApplied Physics Letters
Volume100
Issue number21
DOIs
Publication statusPublished - 2012 May 21
Externally publishedYes

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metal oxide semiconductors
threshold voltage
field effect transistors
degradation
shift
temperature
traps

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

Cite this

Threshold voltage shift and drain current degradation by negative bias temperature instability in Si (110) p-channel metal-oxide-semiconductor field-effect transistor. / Ota, K.; Saitoh, M.; Nakabayashi, Y.; Ishihara, T.; Uchida, Ken; Numata, T.

In: Applied Physics Letters, Vol. 100, No. 21, 212109, 21.05.2012.

Research output: Contribution to journalArticle

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