Throughput enhancement strategy of maskless electron beam direct writing for logic device

R. Inanami, S. Magoshi, S. Kousai, M. Hamada, T. Takayanagi, K. Sugihara, K. Okumura, T. Kuroda

Research output: Contribution to journalConference article

36 Citations (Scopus)

Abstract

A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P&R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.

Original languageEnglish
Pages (from-to)833-836
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 2000 Dec 1
Externally publishedYes
Event2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
Duration: 2000 Dec 102000 Dec 13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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  • Cite this

    Inanami, R., Magoshi, S., Kousai, S., Hamada, M., Takayanagi, T., Sugihara, K., Okumura, K., & Kuroda, T. (2000). Throughput enhancement strategy of maskless electron beam direct writing for logic device. Technical Digest - International Electron Devices Meeting, 833-836.