Throughput enhancement strategy of maskless electron beam direct writing for logic device

R. Inanami, S. Magoshi, S. Kousai, M. Hamada, T. Takayanagi, K. Sugihara, K. Okumura, Tadahiro Kuroda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

36 Citations (Scopus)

Abstract

A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P&R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.

Original languageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting
Pages833-836
Number of pages4
Publication statusPublished - 2000
Externally publishedYes
Event2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
Duration: 2000 Dec 102000 Dec 13

Other

Other2000 IEEE International Electron Devices Meeting
CountryUnited States
CitySan Francisco, CA
Period00/12/1000/12/13

Fingerprint

Logic devices
Electron beams
Throughput
Semiconductor materials
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Inanami, R., Magoshi, S., Kousai, S., Hamada, M., Takayanagi, T., Sugihara, K., ... Kuroda, T. (2000). Throughput enhancement strategy of maskless electron beam direct writing for logic device. In Technical Digest - International Electron Devices Meeting (pp. 833-836)

Throughput enhancement strategy of maskless electron beam direct writing for logic device. / Inanami, R.; Magoshi, S.; Kousai, S.; Hamada, M.; Takayanagi, T.; Sugihara, K.; Okumura, K.; Kuroda, Tadahiro.

Technical Digest - International Electron Devices Meeting. 2000. p. 833-836.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Inanami, R, Magoshi, S, Kousai, S, Hamada, M, Takayanagi, T, Sugihara, K, Okumura, K & Kuroda, T 2000, Throughput enhancement strategy of maskless electron beam direct writing for logic device. in Technical Digest - International Electron Devices Meeting. pp. 833-836, 2000 IEEE International Electron Devices Meeting, San Francisco, CA, United States, 00/12/10.
Inanami R, Magoshi S, Kousai S, Hamada M, Takayanagi T, Sugihara K et al. Throughput enhancement strategy of maskless electron beam direct writing for logic device. In Technical Digest - International Electron Devices Meeting. 2000. p. 833-836
Inanami, R. ; Magoshi, S. ; Kousai, S. ; Hamada, M. ; Takayanagi, T. ; Sugihara, K. ; Okumura, K. ; Kuroda, Tadahiro. / Throughput enhancement strategy of maskless electron beam direct writing for logic device. Technical Digest - International Electron Devices Meeting. 2000. pp. 833-836
@inproceedings{ada82c0924944f8c9b045117474fb40a,
title = "Throughput enhancement strategy of maskless electron beam direct writing for logic device",
abstract = "A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P&R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10{\%}.",
author = "R. Inanami and S. Magoshi and S. Kousai and M. Hamada and T. Takayanagi and K. Sugihara and K. Okumura and Tadahiro Kuroda",
year = "2000",
language = "English",
pages = "833--836",
booktitle = "Technical Digest - International Electron Devices Meeting",

}

TY - GEN

T1 - Throughput enhancement strategy of maskless electron beam direct writing for logic device

AU - Inanami, R.

AU - Magoshi, S.

AU - Kousai, S.

AU - Hamada, M.

AU - Takayanagi, T.

AU - Sugihara, K.

AU - Okumura, K.

AU - Kuroda, Tadahiro

PY - 2000

Y1 - 2000

N2 - A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P&R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.

AB - A pattern design method for semiconductor circuits in logic device was developed, which realized an electron beam (EB) exposure with sufficient throughput. The number of EB shots can be decreased by repeating logic synthesis and P&R (place and route) by removing usable standard cells (SCs). By using the design method, a functional block with about 140 kGates could be generated with only 17 SCs, and the minimum number of EB shots was attained with 24 SCs. The increase in the total area of SCs and the consumed power of the chip was only 10%.

UR - http://www.scopus.com/inward/record.url?scp=0034454065&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034454065&partnerID=8YFLogxK

M3 - Conference contribution

SP - 833

EP - 836

BT - Technical Digest - International Electron Devices Meeting

ER -